64-bit floating-point multiply accumulator and method for processing flowing meter of floating-point operation thereof

Abstract

The invention discloses a 64-bit floating-point multiply accumulator and a method for processing the flowing meter of floating-point operation thereof. A first index processing unit of the multiply accumulator is used for calculating the index difference in floating-point multiplication-addition and floating-point multiplication operations; a first symbol processing unit is used for judging the symbol of results of the floating-point multiplication-addition and floating-point multiplication operations and judging whether to conduct effective subtraction; a second index processing unit thereof is used for processing the index of operands when only the addition operations are conducted; a second symbol processing unit is used for processing the symbol of operands when only the addition operations are conducted; and an index and symbol selector thereof is used for selecting the results of the first index processing unit and the first symbol processing unit or selecting the results of the second index processing unit and the second symbol processing unit, and judging the index difference d, wherein if d is equal to 0,1, 2, or minus 1 and the valid subtraction is conducted, the operations are conducted through a CLOSE path, and if not, the operations are conducted through an FAR path, so as to reduce the time delay of the multiply accumulator.

Description

technical field [0001] The present invention relates to the technical field of microprocessors, in particular to a floating-point multiplication-add component design technology in the microprocessor, and in particular to a 64-bit floating-point multiplication-adder and a floating-point operation pipeline beat processing method thereof. Background technique [0002] In order to achieve the high efficiency of floating-point calculation, a floating-point arithmetic unit floating-point multiply-adder is used in many microprocessors to realize continuous floating-point multiplication and addition. The floating-point multiply-adder performs (A×B)+C operation in one instruction, and there is only one rounding operation, thus improving the accuracy of the calculation. When the operand C in the multiplication and addition instruction is set to 0, the multiplication instruction is executed, and when the operand B is set to 1, the addition instruction is executed, so the floating-point...

AI Technical Summary

Problems solved by technology

In Reference 6, the two-path method proposed based on the difference in exponents can reduce the delay to a certain extent compared with the traditional multiplier-adder, but due to the existence of a large-scale (106bit) shifter and the calculation of rounding bits Complexity makes the delay of the FAR path a bottleneck

Compared with the 2-path method, the 3-path method in Reference 5 can reduce the delay of the multiplier-adder on a large scale, but at the same time, due to the complexity of the path division, it increases a large amount of area overhead compared to the 2-path method.

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