Method for positioning trigger point accurately in multi-ADC parallel high-speed data acquisition system

Abstract

The invention discloses a method for positioning a trigger point accurately in a multi-ADC parallel high-speed data acquisition system, which comprises the steps of: (1) measuring the duration between a rising edge of a trigger signal and a rising edge of a data synchronous clock, and dividing the duration by an equivalent sampling clock cycle to obtain a specific position of the trigger point in multi-channel data; and (2) calculating the number of losing data when a waveform is drawn every time according to the specific position of the trigger point in the multi-channel data, and drawing the waveform according to sampling data after data losing. Compared with the prior art, the positioning of the trigger point in the specific position of the multi-channel data is uncorrelated with a trigger mode, the duration between the rising edge of the trigger signal and the rising edge of the data synchronous clock is only measured, and thus the position of the trigger point can be positioned accurately without being influenced by the trigger mode.

Description

technical field [0001] The invention relates to the positioning of trigger points in a data acquisition system, in particular to a method for precise positioning of trigger points in a multi-ADC parallel high-speed data acquisition system to stably display waveforms. Background technique [0002] In the high-speed data acquisition system, due to the limitation of the ADC sampling rate of the analog-to-digital conversion chip, multi-chip ADCs are usually used, and parallel time-alternating sampling technology is used to equivalently increase the sampling rate of the system. Since the sampling data output by multiple ADCs has a high rate, it is generally difficult for subsequent data processing devices such as FPGAs to directly process such high-speed data due to internal operating frequency. Therefore, after the sampling data enters the FPGA, the DDR double-edge sampling technology is used to divide one channel of data into two or more channels of data with a lower rate. In ...

AI Technical Summary

Problems solved by technology

However, in some special cases, for example, the trigger selection mode is external trigger, or the signal channel selects through, but the trigger channel selects AC coupling, and at the same time, there is a certain DC component superimposed in the input signal, or there is a phase difference between the measured signal and the trigger signal. , the sampling data at this time may be larger or smaller than the trigger level value as a whole, that is, the two will not intersect at all, and the software query algorithm will completely lose its effect

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