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Simulation generation method for parallel interleaver

An interleaver and row number technology, applied in the field of parallel interleaver generation, can solve problems such as memory conflicts, and achieve the effects of reducing time delay, low algorithm complexity, and improving system throughput

Inactive Publication Date: 2010-06-02
TSINGHUA UNIV
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  • Claims
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Problems solved by technology

[0016] However, memory conflicts may sometimes occur depending on the interleave pattern and the division method of the RAM block

Method used

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  • Simulation generation method for parallel interleaver
  • Simulation generation method for parallel interleaver
  • Simulation generation method for parallel interleaver

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Embodiment

[0065] Embodiment: In this embodiment, the number of interleavers K=2, the degree of parallelism M=4, the length of the sequence to be interleaved N=24, and thus the generation of parallel interleaving patterns when the memory length W=N / M=6 is obtained. Wherein, in the step (3), the generation of the basic interleaving vector adopts the QPP interleaver in 3GPP Realse8, and the input position index i and the output position index π(i) adopt the following relational expression:

[0066] π(i)=(f 1 i+f 2 i 2 )modW,

[0067] parameter f 1 and f 2 Depends on the block size W, which can be obtained by looking up the interleaver parameter table in the Turbo code in the 3GPP Realse8 standard (such as when W=40, f 1 = 3, f 2 =10).

[0068] The signal address sequence before interleaving is set to be arranged in the order of 1-24, and the generation of the interleaving pattern includes the following steps:

[0069] Step (1) Make a two-dimensional arrangement of 4 rows and 6 colu...

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Abstract

The invention discloses a simulation generation method for a parallel interleaver, and belongs to the technical field of mobile wireless data transmission. The method is characterized by comprising the following steps: dividing an RAM into M independent access blocks, and setting the number of storage units of each block as W so as to acquire a block address (block number and in-block address) of each storage unit; equally dividing sequences to be interleaved into M sections in order, and setting the number of symbols of each section as W so as to acquire a section address (section number and in-section address) of each symbol; using the generated different random sequences as rows of interleaving patterns, and mapping the section number of each section address to the block number of the block address; on the basics, generating a basic interleaving vector according to the length of the memory, acquiring rows of interleaving patterns of different interleavers through cyclic shift for the basic interleaving vector, and mapping the in-section address of each section address to the in-block address of the corresponding block; and writing the symbols of the section address into the storage units of the corresponding block address, and synchronously reading the symbols out in address order. The method saves the storage resource and effectively reduces the time delay.

Description

technical field [0001] The invention belongs to the technical field of mobile wireless data transmission, in particular to a method for generating a parallel interleaver. Background technique [0002] Interleaving is a technology used for data processing in communication systems. In essence, an interleaver is a device that can change the information structure to the greatest extent without changing the information content. Traditionally, it is to discretize the error code, make the burst error channel into a discrete error channel, and correct the random discrete error at the receiving end, thereby improving the system performance. [0003] The function of interleaving, in essence, is to exchange the position of each symbol in the input signal sequence according to a certain mapping relationship to obtain the corresponding output signal sequence, and the position of each symbol in the input signal sequence corresponding to the output signal sequence is interleaving pattern....

Claims

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Application Information

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IPC IPC(8): H04L1/00G06F17/50
Inventor 周世东陈翔张秀军肖立民吴双李漪
Owner TSINGHUA UNIV
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