Hardware transactional nesting method for supporting rollback of conditional part

A technology of hardware transactions and processing methods, applied in the direction of multi-programming devices, etc., can solve problems such as large rollback overhead and high conflict probability, and achieve the effects of obvious performance improvement, system performance improvement, and programmability improvement

Inactive Publication Date: 2010-06-16
BEIHANG UNIV
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Problems solved by technology

The commonly used processing method in hardware transactional storage systems is the flatten model, that is, a transaction and its inner transactions are treated as one transaction, and the commit operation is performed when the outermost transaction ends, and when the nested tran

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  • Hardware transactional nesting method for supporting rollback of conditional part
  • Hardware transactional nesting method for supporting rollback of conditional part
  • Hardware transactional nesting method for supporting rollback of conditional part

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Embodiment Construction

[0039] The present invention will be further described in detail below in conjunction with the accompanying drawings.

[0040] In the present invention, nested transactions are composed of multiple transaction layers. For the convenience of description, the first-level transaction is recorded as T 1 , the second-level transaction is denoted as T 2 , and the third-level transaction is denoted as T 3 ,..., the transaction at the nth layer is denoted as T n , then the nested transaction adopts the mathematical set expression form T={T 1 ,T 2 ,T 3 ,...,T n}. First layer transaction T 1 Also known as the outermost transaction. nth layer transaction T n Also known as the innermost transaction. The conflicting transaction is recorded as T c , referred to as the conflict layer transaction T c , c represents the conflict layer transaction T c where the number of layers.

[0041] The present invention is a hardware transaction nesting processing method that supports condi...

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Abstract

The invention discloses a hardware transactional nesting method for supporting rollback of a conditional part. According to the method, a global data set is maintained by each layer of nesting transaction, and the access condition of each layer of transaction to the data is recorded in the set. The method comprises the following steps: if the data set accessed by a conflict layer transaction has no superposition with the data sets of other transactions before the conflict layer transaction, rolling back to the initial position of the conflict layer transaction; and if the conflict layer transaction has the same conflict variable with the data set of the transaction before the conflict layer transaction, rolling back to the initial position of the first appearing transaction with the same conflict variable. The method of the invention reduces the great cost required for rolling back the transaction to the outmost layer in a closed nesting mode, and effectively improves the transactional nesting performance without greatly increasing the complexity of the hardware.

Description

technical field [0001] The invention relates to a multi-thread parallel programming method belonging to a computer system structure, in particular to a hardware transaction nesting processing method supporting conditional partial rollback. Background technique [0002] With the rapid development of multi-core processors, programs need to use more multi-threading mechanisms to make full use of multi-core resources to improve program performance. The traditional concurrent programming mode realizes the synchronization and mutual exclusion between processes / threads through mechanisms such as locks and semaphores. Improper use of synchronization or mutual exclusion often leads to program performance degradation and deadlocks, which makes it difficult and difficult to write multi-core concurrent programs. The debugging complexity is much higher than that of serial programs. [0003] Transactional Memory (TM) is a technology aimed at improving the programmability of parallel syst...

Claims

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Application Information

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IPC IPC(8): G06F9/46
Inventor 刘轶吴名瑜张翠钱德沛
Owner BEIHANG UNIV
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