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Method for dynamically allocating on-chip heterogeneous memory resources by utilizing virtual memory mechanism

A heterogeneous storage and dynamic allocation technology, applied in memory address/allocation/relocation, memory systems, instruments, etc., can solve problems such as high power consumption, large occupied area, unpredictable program execution time, etc., and achieve the goal of reducing the number of times Effect

Inactive Publication Date: 2012-07-04
SOUTHEAST UNIV
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AI Technical Summary

Problems solved by technology

However, the shortcomings of Cache, such as high power consumption, large footprint, and unpredictable program execution time, have always limited its wide application in embedded systems.
[0008] So far, there is no related research involving the unified analysis of program data, including global data, constant pool, heap and stack, and dynamically mapping them into SPM

Method used

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  • Method for dynamically allocating on-chip heterogeneous memory resources by utilizing virtual memory mechanism
  • Method for dynamically allocating on-chip heterogeneous memory resources by utilizing virtual memory mechanism
  • Method for dynamically allocating on-chip heterogeneous memory resources by utilizing virtual memory mechanism

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Embodiment Construction

[0037] The present invention will be described in further detail below with reference to the accompanying drawings and specific embodiments.

[0038] The present invention obtains the time and space distribution of data Cache missing by tracking the data Cache access during the execution of the application program, and then obtains the time slot conflict graph of the data Cache from the distribution, including global data, constant pool data, stack data and heap data. data. A conflict graph is a vector diagram that quantitatively describes the replacement relationship between different program contents that are mapped to the same cache line. By mathematical abstraction of cache time slot conflicts, the state of each data page when the total energy consumption of the system is optimal can be determined by using the integer nonlinear programming method, and the page number of the data page with the most optimization value in each time slot can be obtained. . Then, according to...

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Abstract

The invention discloses a method for dynamically allocating on-chip heterogeneous memory resources by utilizing a virtual memory mechanism, comprising the following steps of: analyzing the time and space distribution of data sections (comprising global data, stack data, pile data and constant pool data) with data Cache conflicts caused by high frequency by adopting a time slot analyzing method, then obtaining the time slot conflict diagram of the data Cache by the distribution and carrying out mathematical abstraction for the time slot conflict diagram. According to the target function of energy consumption and the target function of performance, a program part to be optimized is selected by using an integer nonlinear programming method and then is dynamically remapped in an on-chip data SPM (Scratch-pad Memory) by utilizing clock interrupt, and thereby, the extra memory access caused by the data Cache conflicts can be avoided. The method can reduce the energy consumption of a system and enhance the performance of the system due to the full utilization of on-chip heterogeneous memory.

Description

technical field [0001] The invention relates to the field of embedded on-chip memory, in particular to a method for dynamically allocating on-chip heterogeneous storage resources (data parts of Cache and SPM) by using a virtual memory mechanism. Background technique [0002] With the development of microelectronics technology, the embedded computing platform based on SoC (System-on-a-Chip) is becoming more and more mature. However, due to the growing gap between processor speed and external memory speed, the SoC memory subsystem has become a bottleneck in system performance, power consumption and cost. Therefore, how to optimize the architecture and management strategy of the storage subsystem has always been a hotspot of embedded research. [0003] As a traditional on-chip memory, the Cache is managed by hardware and is transparent to software in most cases, and can automatically load frequently accessed instructions and data into the on-chip memory. However, Cache's high...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F12/08G06F13/28G06F12/0866
CPCY02B60/1225Y02B60/1228Y02B60/1235Y02D10/00
Inventor 凌明张阳梅晨王欢武建平
Owner SOUTHEAST UNIV
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