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Signal processor and signal processing method

A signal processing device and a technology for testing signals, applied in DC level restoration devices/bias distortion correction, digital transmission systems, electrical components, etc., can solve problems such as performance degradation

Active Publication Date: 2010-06-16
NEC CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

However, although the required performance level has increased in recent years due to the increase in the speed of communication, the performance issues mentioned at the beginning have conversely become more difficult due to the restrictions on the circuit structure caused by the direct conversion of the architecture and the lower voltage of the processor. Deterioration trend

Method used

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no. 1 approach

[0113] figure 1 It is a diagram showing the configuration of the signal processing device according to the first embodiment of the present invention. refer to figure 1 It can be seen that the signal processing device according to one embodiment of the present invention includes a test signal generation unit 10, a DC offset IQ mismatch estimation unit 17, a quadrature modulator 11, a wave detector 12, a comparison and judgment unit 13, and a control unit 14. , an adjustment value storage unit 15 , and a compensation value derivation unit 16 . Briefly speaking, each of the above-mentioned parts executes the following processes and operations. The test signal generator 10 generates a first test signal (I 1 , Q 1 ) (wherein, in (I, Q), I represents the in-phase component signal, Q represents the quadrature component signal) and the second test signal (I 2 , Q 2 ) and supply them to the quadrature modulator 11. Quadrature modulator 11 to the first test signal (I 1 , Q 1 ...

no. 2 approach

[0119] image 3 It is a figure which shows the signal processing apparatus of 2nd Embodiment of this invention. In addition to this embodiment figure 1 In addition to the structure of the signal processing device, it also includes: a transmission baseband signal generation unit 18 that generates signal components of the I channel and Q channel from the transmission signal, and a unit 17 that estimates the DC offset and the IQ mismatch and inputs the transmission baseband signal. Compensation is performed and the compensated signal is supplied to the first compensation section 19 of the quadrature modulator 11 . The test signal generated by the test signal generating unit 10 is supplied to the quadrature modulator 11 indirectly via the first compensating unit 19 . In addition, it includes: select one of the transmission baseband signal and the test signal and output it to the first switch unit 30 of the first compensating part 19, convert the in-phase component (I) from the ...

no. 3 approach

[0125] Figure 4 is a diagram showing a signal processing device according to a third embodiment of the present invention. In addition to this embodiment figure 1 In addition to the structure of the signal processing device, it also includes: a transmission baseband signal generation unit 18 that generates signal components of the I channel and Q channel from the transmission signal, and a unit 17 that estimates the DC offset and the IQ mismatch and inputs the transmission baseband signal. Compensation is performed and the compensated signal is supplied to the first compensation section 19 of the quadrature modulator 11 . In addition, it includes: the third DAC 42 and the fourth DAC 43 which convert the output of the first compensating part 19 into an analog signal, the fifth DAC 44 and the sixth DAC which convert the test signal generated by the test signal generating part 10 into an analog signal 45. Select one of the output of the third DAC 42 and the output of the fifth...

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Abstract

A modulator (radio unit, modulation method) for reducing DC offset and an error of a comparator with a simple structure for accurately compensating a mismatch between an amplitude and a phase of an IQ signal. A modulation signal generated by supplying a test signal to an orthogonal modulator is envelope-detected, and a control part (14) derives an adjustment value and a compensation value based on determination results obtained by further comparing and determining the detection results. Based on the derived compensation value, a means (17) estimates the DC offset and the IQ mismatch of the orthogonal modulator. The test signal includes a first set containing a first test signal (I1, Q1) and a second test signal (I2, Q2) having a predetermined relation with the first test signal, and a second set with in-phase and orthogonal components having a predetermined relation with the first set. The control part (14) acquires the compensation value based on a first adjustment value and a second adjustment value respectively derived corresponding to the first set and the second set.

Description

technical field [0001] (About the related application) [0002] The present invention claims priority from Japanese Patent Application No. 2007-181019 (filed on Jul. 10, 2007 ), the entire contents of which are incorporated herein by reference. [0003] The present invention relates to a frequency conversion device or a transmission unit for communication accompanied by frequency conversion. Background technique [0004] In a quadrature modulator and a wireless transmission device using the quadrature modulator, suppression of carrier leakage and prevention of deterioration of modulation accuracy are necessary to ensure communication quality and comply with legal regulations. However, in recent years, the required performance level has increased with the speeding up of communications, but the performance issues mentioned at the beginning are conversely due to the limitation of the circuit structure caused by the direct conversion of the architecture and the reduction of the...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H04L27/00
CPCH04L27/364H04L25/06
Inventor 柳泽洁松野典朗
Owner NEC CORP
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