Film electroluminescence display driver
A display and electroluminescence technology, applied in static indicators, instruments, etc., can solve the problems of power consumption, complex process, small viewing angle, etc., and achieve the effect of improving circuit stability, simplifying circuit structure, and solving floating problems.
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Embodiment 1 pic 1,DVI1 and 1 FPGA2,DVI1 to FPGA2,FPGA246 and 3 to 1 TFEL7, 1 5。FPGA2DVI1TFEL,463,TFEL7,TFEL150V(TFEL),。 approach ,, corresponding , and 1 , other , 1 1 , 1 1 , 1 1 ,。 Embodiment 2
[0030] Embodiment one: if figure 1 As shown, the thin film electroluminescent display driver includes a DVI transmission circuit 1 and an FPGA controller 2, and is characterized in that the video signal is connected to the FPGA controller 2 through the DVI transmission circuit 1, and the two outputs of the FPGA controller 2 After the optocoupler circuit isolation module 4, it is respectively connected to a TFEL display screen 7 of thin film electroluminescence material through the row driver chip 6 and the column driver chip 3, and a driving power module 5 provides working power for each group of devices. The FPGA controller 2 receives the DVI signal 1 and outputs the TFEL control signal, controls the row 6 column 3 driver chips after isolation by the photocoupler 4, and outputs high voltage alternately at different times of the positive and negative voltage fields to act on the TFEL screen 7, when applied When the voltage difference between the rows and columns of the TFEL sc...
Embodiment 3
[0052] Embodiment three: present embodiment is identical with embodiment two, and special point is that the software design of TFEL display driver is as follows:
[0053] The TFEL display driver software includes two parts: TFEL display driver and DVI video signal transmission software.
[0054] , TFEL display driver programming software:
[0055] In the quartus software launched by Altera Corporation, two programming languages, VHDL and Verilog HDL, are used to write the software.
[0056] 1) According to the internal structure of the row driver chip HV7224 such as Figure 9 As shown, when the data reset terminal (DRIO) is at a logic high level, the HV7224 chip will convert all internal outputs to zero. Simultaneously, the output of the conversion register begins to shift the logic high level from the least significant bit to the most significant bit. DRIO can be activated at any time. The DIR and SHIFT terminals can control the direction of data transmission. When DIR is...
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