Method for dynamically distributing isomerism storage resources on instruction parcel based on virtual memory mechanism

Abstract

The invention discloses a method for dynamically distributing isomerism storage resources on an instruction parcel based on a virtual memory mechanism, wherein the storage resources on the instruction parcel comprising command Cache and command SPM are fully utilized. In the invention, time slot analyzing method is adopted to analyze the time and space distribution hit and missing by command Cache caused by high frequency to obtain time slot access map of the command Cache and perform mathematical abstraction to the time slot access map. According to energy consumption target function and performance target function, the program command parts needing optimization in different time slots are selected by utilizing integer non-linear programming method, different program phases are divided by utilizing a clock module, and when clock is suspended, command pages with optimizing value are dynamically remapped into a command SPM memory by utilizing a command SPM controller, thus avoiding additional access and memory caused by command Cache conflict and obtaining energy consumption gain from once access energy consumption difference of Cache and SPM. In the method, isomerism storage on instruction parcel is fully utilized, thus reducing system energy consumption and improving system performance.

Description

technical field [0001] The invention relates to the field of embedded on-chip memory, in particular to a method for dynamically allocating instruction on-chip heterogeneous storage resources (including instruction Cache and instruction SPM) based on a virtual memory mechanism. Background technique [0002] With the development of microelectronic technology, the embedded computing platform based on SoC (System-on-a-Chip) is becoming more and more mature. However, due to the increasing gap between processor speed and external memory speed, the SoC memory subsystem has become the bottleneck of system performance, power consumption and cost. Therefore, how to optimize the architecture and management strategy of the storage subsystem has always been a hot spot in embedded research. [0003] As a traditional on-chip memory, Cache is managed by hardware, transparent to software in most cases, and can automatically load frequently accessed instructions and data into the on-chip mem...

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Problems solved by technology

[0008] The purpose of the present invention is to overcome the deficiencies of the existing on-chip storage subsystem, provide a method for dynamically allocating heterogeneous storage resources on the instruction chip based on the virtual memory mechanism, and use the instruction SPM memory with less capacity to buffer frequent access and easy access during program execution. Programs that cause instruction cache conflicts, optimize the instruction part of the program, thereby increasing the speed of the microprocessor and reducing system energy consumption

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