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Semiconductor integrated circuit device

A technology of integrated circuits and semiconductors, applied in the field of layout structure, can solve the problems of reduced wiring size accuracy, broken wires, and narrowed wiring width, and achieve the effects of reducing data volume, shortening processing time, and shortening OPC correction processing time

Active Publication Date: 2010-07-21
SOCIONEXT INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The optical proximity effect leads to a decrease in the accuracy of the wiring size
For this reason, depending on the wiring interval, the wiring width will be smaller than the specified value due to the influence of the optical proximity effect, and there may be a possibility of disconnection depending on the situation.

Method used

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  • Semiconductor integrated circuit device
  • Semiconductor integrated circuit device
  • Semiconductor integrated circuit device

Examples

Experimental program
Comparison scheme
Effect test

no. 1 approach

[0041] figure 1 It is a layout plan view showing the structure of the semiconductor integrated circuit device according to the first embodiment. exist figure 1 In the structure of , cell A as the first standard cell and cell B as the second standard cell are adjacent at the cell boundary line F1 extending along the first direction (the longitudinal direction in the drawing).

[0042] The unit structures of unit A and unit B are different from each other. In the cell A, PMOS transistors P1, P2 and NMOS transistors N1, N2 are arranged. A power supply voltage is supplied to the sources of the PMOS transistors P1 and P2 through metal wirings m3 and m4 drawn from the power supply wiring m1 . The drains of the PMOS transistors P1 and P2 are shared, and are connected to the drain of the NMOS transistor N1 through the metal interconnection m5. This metal wiring m5 constitutes the output of the cell A. A ground voltage is supplied to the source of the NMOS transistor N2 through th...

no. 2 approach

[0059] Figure 4 It is a layout plan view showing the structure of the semiconductor integrated circuit device according to the second embodiment. exist Figure 4 In the structure of , cell A as the first standard cell and cell B as the second standard cell are adjacent at the cell boundary line F1 extending along the first direction (the longitudinal direction in the drawing).

[0060] The unit structures of unit A and unit B are different from each other. In the cell A, PMOS transistors P1, P2 and NMOS transistors N1, N2 are arranged. The sources of the PMOS transistors P1 and P2 are shared, and a power supply voltage is supplied through a metal wiring m3 drawn from the power supply wiring m1. The drains of the PMOS transistors P1 and P2 are connected by a metal interconnection m4, and are also connected to the drains of the NMOS transistors N1 and N2. This metal wiring m4 constitutes the output of the cell A. The sources of the NMOS transistors N1 and N2 are shared, an...

no. 3 approach

[0074] Figure 7 It is a layout plan view showing the structure of the semiconductor integrated circuit device according to the third embodiment. exist Figure 7 In the structure of , cell A as the first standard cell and cell B as the second standard cell are adjacent at the cell boundary line F1 extending along the first direction (the longitudinal direction in the drawing).

[0075] The unit structures of unit A and unit B are different from each other. In the cell A, PMOS transistors P1, P2 and NMOS transistors N1, N2 are arranged. Sources of the PMOS transistors P1 and P2 are supplied with a power supply voltage through metal wiring m3 and m4 drawn from the power supply wiring m1. The drains of the PMOS transistors P1 and P2 are shared, and are connected to the drain of the NMOS transistor N1 through the metal interconnection m5. This metal wiring m5 constitutes the output of the cell A. The source of the NMOS transistor N2 is supplied with a ground voltage through t...

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PUM

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Abstract

Provided is a semiconductor integrated circuit layout structure wherein thinning and disconnection of a metal wiring close to a cell boundary line can be eliminated without increasing data quantity and processing time required for OPC correction. A cell (A) and a cell (B) are adjacent to each other on a cell boundary line (F1). Wiring regions for metal wirings (m4, m6, m7, m9) are arranged such that no other wiring region exists between such wiring regions and the cell boundary line (F1) and that the wiring regions are substantially line-symmetric with the cell boundary line (F1) as a symmetric axis. Sides (g1, g2, g3, g4) of diffusion regions on the side of the cell boundary line (F1) are asymmetric with respect to the cell boundary line (F).

Description

technical field [0001] The present invention relates to a layout structure of a semiconductor integrated circuit effective for improving the dimensional accuracy of a wiring pattern. Background technique [0002] As the miniaturization advances in the miniaturization of the wiring width, it becomes impossible to ignore the change in the wiring width due to the optical proximity effect (proximity effect). The so-called optical proximity effect is a phenomenon in which the completion value of the wiring width varies depending on the distance to the adjacent wiring. The optical proximity effect leads to a reduction in the accuracy of wiring dimensions. For this reason, depending on the wiring interval, the wiring width may be smaller than the specified value due to the influence of the optical proximity effect, and there may be a possibility of disconnection in some cases. [0003] Therefore, the correction of the influence of the optical proximity effect based on OPC (Optica...

Claims

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Application Information

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IPC IPC(8): H01L21/82G03F1/08
CPCH01L27/11807H01L27/0207
Inventor 池上智朗西村英敏中西和幸
Owner SOCIONEXT INC
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