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Stacked multi-encapsulation structure device, semiconductor encapsulation structure and manufacturing method thereof

A manufacturing method and semiconductor technology, applied in the direction of semiconductor/solid-state device manufacturing, semiconductor devices, semiconductor/solid-state device components, etc., can solve the problem of not having an intermediate substrate or a substrate, etc.

Inactive Publication Date: 2010-08-18
ADVANCED SEMICON ENG INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0006] However, the known stacked multi-package structure device 50 does not have any intervening substrate or substrate disposed between the upper package structure 20 and the lower package structure 10 to provide electrical connection or more functions.

Method used

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  • Stacked multi-encapsulation structure device, semiconductor encapsulation structure and manufacturing method thereof
  • Stacked multi-encapsulation structure device, semiconductor encapsulation structure and manufacturing method thereof
  • Stacked multi-encapsulation structure device, semiconductor encapsulation structure and manufacturing method thereof

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0046] refer to figure 2 , which shows a stacked multi-package device (Package On Package; POP) 200 according to an embodiment of the present invention. The stacked multi-package structure device 200 includes a lower package structure 210 and an upper package structure 220 .

[0047] The lower packaging structure 210 includes a first chip 214 fixed and electrically connected to an upper surface 242 of a first substrate 212 . The first substrate 212 has an upper metal layer and a lower metal layer, which can be patterned to provide appropriate circuitry, and are electrically connected to each other through plated through holes. An interposer 230 is disposed on the first chip 214 and electrically connected to the upper surface 242 of the first substrate 212 . The intermediary substrate 230 can be a circuit board or a substrate, and the substrate can be a plastic substrate or a silicon substrate. The intermediary substrate 230 has an upper surface 236 and a lower surface 238 ,...

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PUM

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Abstract

The invention relates to a semiconductor encapsulation structure which comprises a baseplate, a chip, an intermediary baseplate and a sealant compound; wherein the chip is electrically connected to the upper surface of the baseplate; the intermediary baseplate is arranged on the chip and electrically connected to the upper surface of the baseplate; the intermediary baseplate contains at least one buried assembly and a plurality of electric contacts, wherein the buried assembly is positioned between the upper surface and the lower surface of the intermediary baseplate, and the electric contacts are positioned on the upper surface of the intermediary baseplate; the sealant compound coats the chip and covers the upper surface of the baseplate and the lower surface of the intermediary baseplate.

Description

technical field [0001] The present invention relates to a stacked multi-package device, and more particularly to a lower package structure of a stacked multi-package device including an intermediary substrate. Background technique [0002] At present, the stacked multi-package structure (Package on Package; POP) device mainly refers to disposing one semiconductor package structure on another semiconductor package structure, and its basic purpose is to increase the density to produce greater functions per unit space and better regional performance, thereby reducing the total area and cost of the entire stacked multi-package construction device. [0003] Referring to FIG. 1 , it shows a structure of a known stacked multi-package construction device 50 , that is, two stacked multi-package construction modules (Multi-Package Modules; MPMs), which are electrically connected to each other via solder balls 28 . In this stacked multi-package configuration device 50 , the first pack...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L23/492H01L23/31H01L21/50
CPCH01L2224/32225H01L2224/48091H01L2224/48227H01L2224/73265H01L2924/15311
Inventor 余林旺翁承谊
Owner ADVANCED SEMICON ENG INC