Coreless encapsulation substrate and manufacturing method thereof

Abstract

The invention relates to a coreless encapsulation substrate and a manufacturing method thereof. The method for manufacturing the coreless encapsulation substrate comprises the following steps of: (a) providing a carrier plate and a first conducting layer, wherein the carrier plate is provided with a first surface and a second surface, and the first conducting layer is positioned on the first surface of the carrier plate; (b) forming a first built-in line on the first conducting layer; (c) forming a first dielectric layer to cover the first built-in line; (d) removing the carrier plate; (e) removing part of the first conducting layer to form at least one first welding pad; and (f) forming a first solder mask layer to cover the first built-in line and the first dielectric layer and expose the at least one first welding pad. Thus the coreless encapsulation substrate can improve the wiring density of the line, reduce the manufacturing cost and reduce the thickness of products.

Description

technical field [0001] The invention relates to a packaging substrate and a manufacturing method thereof, in particular to a coreless packaging substrate and a manufacturing method thereof. Background technique [0002] refer to figure 1 and figure 2 , showing a manufacturing method of a known packaging substrate. Firstly, a core substrate 11 is provided, and the core substrate 11 includes a core layer 111 , a first circuit layer 112 , a second circuit layer 113 and at least one through hole 114 . The core layer 111 includes a first surface 1111 and a second surface 1112 . The first circuit layer 112 is located on the first surface 1111 of the core layer 111 . The second circuit layer 113 is located on the second surface 1112 of the core layer 111 . The through hole 114 penetrates through the core layer 111 and electrically connects the first circuit layer 112 and the second circuit layer 113 . [0003] Next, a first dielectric layer 12 and a second dielectric layer 1...

AI Technical Summary

Problems solved by technology

The manufacturing method starts from the core substrate 11, which has a certain thickness, so the resulting known packaging substrate 1 has a low wiring density.

In addition, the inner layer structure of the core substrate 11 is completed through processes such as drilling, metal plating, plugging, and circuit forming, which makes the process steps complicated and expensive.

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