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ECC circuit for correcting multi-bit errors

A multi-bit, error technique applied in the field of FPGA

Active Publication Date: 2012-11-21
FUDAN UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, for other situations, such as multiple column errors and L-type errors, since they belong to the same ECC word, the ECC circuit in the Virtex series is powerless

Method used

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  • ECC circuit for correcting multi-bit errors
  • ECC circuit for correcting multi-bit errors
  • ECC circuit for correcting multi-bit errors

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Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0020] The ECC circuit for correcting multi-bit errors proposed by the present invention is valuable in the application of preventing soft errors from damaging FPGAs with an SRAM structure, and should cooperate with the overall process to play a role.

[0021] Utilize the ECC circuit that corrects multi-bit error that the present invention proposes to realize the concrete steps of anti-soft error function as follows image 3 As shown, the specific description is as follows:

[0022] 1) Generate a bit stream with redundant codes. The software expands the generated configuration data by filling every 32 bits with a dummy bit (the value is 0), and then takes every 11 bits of data as an information effective bit unit, and generates 4 bits through the (15, 11) Hamming cyclic code encoder Redundant bit data.

[0023] 2) Bit stream download. Write the redundant bit data into the chip's internal BLOCK RAM, and write the generated configuration data into the chip's internal programm...

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PUM

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Abstract

The invention belongs to the technical field of FPGA, in particular to an ECC circuit applied to an SRAM FPGA device for correcting multi-bit errors. The circuit is formed by connecting a one-out-three MUX, a decoder, an error pattern lookup table and a write-back circuit in turn. The circuit comprises the following flows of: firstly, reading back programmable point information to an ECC register, and outputting the programmable point information to the decoder through the one-out-three MUX according to a certain rule respectively; and meanwhile, outputting redundancy bits stored in a BLOCK RAM inside an FPGA chip and serving as 4 redundancy bits to the decoder, wherein the decoder adopts a (15, 11) Hamming cyclic code decoder. The circuit can correct a plurality of programmable points causing soft errors in the FPGA so that the FPGA has the function of resisting the soft errors, and meanwhile furthest reduces the area overhead.

Description

technical field [0001] The invention belongs to the technical field of FPGA, and in particular relates to a circuit structure for enabling FPGA to have the function of resisting soft errors. In particular, it relates to an ECC circuit structure for correcting multi-bit errors in FPGA. Background technique [0002] FPGA has unique field programmability and general flexibility, circuit functions can be reconfigured, and the design cycle is short, so it is increasingly widely used in defense weaponry, civilian communication, automobile, medical and other fields. However, as the semiconductor process enters the ultra-deep submicron or nanometer scale, the advantages brought by small size, high density and low voltage are facing great challenges-the reduction of noise margin makes the FPGA device based on the SRAM structure extremely vulnerable to bit Flip (bit flips) [1]. This accidental bit flip originating from soft error is due to the injection of high-energy band particles...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H03M13/09
Inventor 谢婧来金梅
Owner FUDAN UNIV