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Mesosynchronous data bus apparatus and method of data transmission

A technology of data and data packets, applied in the fields of electrical digital data processing, climate sustainability, instrumentation, etc., can solve problems such as limiting data bus length and signal transmission speed

Active Publication Date: 2012-10-03
VIOLIN MEMORY INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The total skew will limit the length of the data bus as well as the speed of signal transmission

Method used

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  • Mesosynchronous data bus apparatus and method of data transmission
  • Mesosynchronous data bus apparatus and method of data transmission
  • Mesosynchronous data bus apparatus and method of data transmission

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Embodiment Construction

[0027] Embodiments of the present invention can be better understood with reference to the accompanying drawings, but the described embodiments cannot be used to limit the scope of the present invention. The same reference numerals in the same or different drawings represent the same meaning. Parts can be represented by numbers or abbreviations, or both, and the way to represent parts is just for clarity, so if a part is numbered, and the same part is represented by abbreviations or letters Numerals indicate that such components are to be understood as identical components.

[0028] It is clear to those skilled in the art that the method and device of the present invention can be configured or incorporated into operating instructions that can be executed by software or by hardware. The operating instructions may activate a device, such as a digital processor, that executes the operating instructions to implement the operations of the present invention. Alternatively, the opera...

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Abstract

A memory system is described, where the transmission time of data between memory modules is managed so that the overall time delay between specified points in the memory system is maintained a constant. Each lane of a multilane bus may be separately managed, and a data frame evaluated at the destination module, without a need for deskewing at intermediate modules. The time delay in propagation ofthe data through a module, which may have a switch to route the data, is reduced by operating the data path through the module at one or more submultiples of the bus serial data rate, and selecting the sampling point of the received data so that variations in time delay due to temperature changes or ageing are accommodated.

Description

technical field [0001] The invention relates to the management of distributed clocks in storage systems. Background technique [0002] In a computer system, a central processing unit (CPU, central processor) is used to access program information and data stored in a storage system. There are currently various levels of memory systems available in size, speed, and capability for computer system designers to choose from during the computer system design phase. These memory systems may include cache memory, primary storage, and secondary memory. The cache memory has the characteristics of low latency, high bandwidth, and high cost, and it can be integrated into the CPU. Meanwhile, the cache memory may be a semiconductor device, such as a static random access memory (SRAM, static random access memory). The main memory is also a semiconductor device, such as a dynamic random access memory (DRAM), and the main memory is mainly used to store data and programs with low access prob...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F13/16
CPCG06F13/4243Y02D10/00
Inventor 詹姆斯·H·琼斯凯文·D·德鲁克乔恩·C.R.·贝内特
Owner VIOLIN MEMORY INC