Dual-end static random access memory (SRMA) unit

Abstract

The invention discloses a dual-end SRAM unit. The SRAM unit comprises a complementary metal-oxide-semiconductor (CMOS) inverter, a first p-channel metal oxide semiconductor (PMOS) transistor, a first resistor, a first transmission transistor and a second transmission transistor, wherein the first PMOS transistor is connected with the COMS inverter; the first resistor is connected with the first PMOS transistor; the first transmission transistor is connected with the first PMOS transistor; the second transmission transistor is connected with the CMOS transistor; and the first transmission transistor is a write-operation transmission transistor and the second transmission transistor is a read-operation transmission transistor. The dual-end SRAM unit provided by the invention only comprises 5 transistors, so the area of the dual-end SRAM unit is greatly reduced; and a resistance value of the first resistor is several magnitude orders greater than the resistance value of the conducted first PMOS transistor and the resistance value of the conducted first transmission transistor and smaller than the resistance value of the closed first PMOS transistor and the resistance value of the closed transmission transistor, so operation of writing '0' and operation of writing '1' can be carried out smoothly.

Description

technical field [0001] The invention relates to the technical field of integrated circuits, in particular to a double-terminal SRAM unit which can effectively reduce chip area. Background technique [0002] As the functions of digital integrated circuits are becoming more and more complex and the scale is getting larger and larger, on-chip integrated memory has become a very important part of digital systems. Embedded static random access memory (Static Random Access Memory, SRAM) has become an indispensable and important part of on-chip memory due to its advantages of low power consumption and high speed. SRAM can hold data as long as it is powered, there is no need to constantly refresh it. [0003] The overall structure of SRAM can be divided into two parts: memory bank array and peripheral circuit. Among them, the memory bank array is composed of a pre-charging circuit and a memory cell array; the peripheral circuit is composed of a row and column address decoder, a re...

AI Technical Summary

Problems solved by technology

[0010] The purpose of the present invention is to provide a double-terminal SRAM unit to solve the problem that the existing double-terminal 8T SRAM unit is too large, which is not conducive to improving the integration of integrated circuits

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