Method for erasing single-transistor memory array

Abstract

The invention discloses a method for erasing a single-transistor memory array, which comprises the following steps of: erasing a threshold voltage of each target memory unit to be below an upper limit value of a given threshold voltage, and finally enabling the threshold voltages of all the target memory units of the signal-transistor memory array under the erasing state to be distributed within a give safety window range by utilizing the characteristic that the hot carrier injection property changes along with difference of threshold voltages of the memory units; injecting hot electrons into the over-erased target memory units which have lower threshold voltages, so that the threshold voltages of the over-erased target memory units are increased to be above a lower limit value of the given threshold value for avoiding read interference; and injecting electron holes to the weakly-erased target memory units which have higher threshold voltages into holes, so that the threshold voltages of the weakly-erased target memory units are converged to be below the upper limit value of the given threshold voltage, so that enough erasing windows can be provided for meeting the requirement on data retention reliability.

Description

technical field [0001] The invention relates to semiconductor technology, in particular to a method for erasing a single-tube memory array. Background technique [0002] Commonly used non-volatile flash memories include floating gate memories, SONOS (Silicon-Oxide-Nitride-Oxide-Silicon) memories, nanocrystal memories, and the like. The device structure of a non-volatile flash memory cell is similar to that of a common CMOS device. The only difference is that the oxide between the gate and the substrate in the CMOS structure has become a stacked structure of insulating layer-charge trapping layer-insulating layer The purpose of storing information is achieved by injecting or erasing charges into the charge trapping layer in the middle of the stacked structure. [0003] In non-volatile single-transistor memory arrays, such as figure 1 As shown, a column of the memory is formed by parallel connection of multiple storage tubes sharing the source and drain. A single storage tub...

AI Technical Summary

Problems solved by technology

When the F-N tunneling effect is weakly written to the over-erased memory cell, under the action of the positive electric field from the gate to the substrate, the same as the over-erased memory cell with a low threshold voltage, the threshold voltage is normal or even high The normally erased memory cells are also affected by the substrate-gate injected electron current, such as image 3 , Figure 4 As shown, after electrons are injected from the substrate into the charge-trapping layer, the threshold voltage is raised monotonously, causing the erasing window of some memory cells in the single-transistor memory array to be too low, such as Figure 5 shown

These memory cells with too low erasing window may not have enough erasing window to meet the requirements of data retention reliability, and the process of F-N tunneling effect on the over-erased memory cells is to erase them all The threshold voltage of the target memory cell is greater than the given erase reference lower limit value, and the target memory cell with a smaller erase window (higher threshold voltage) lacks effective monitoring and adjustment means, which increases due to the erasure window Risk of reliability failure due to too small

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