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Storage unit for static random access memory and static random access memory

A static random, storage unit technology, applied in the field of memory, can solve problems such as read interference, achieve the effect of increasing redundancy, improving stability, and avoiding the phenomenon of read interference

Active Publication Date: 2018-03-06
SEMICON MFG INT (SHANGHAI) CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0010] The purpose of the present invention is to provide a storage unit and SRAM for SRAM, to solve the problem that read interference is prone to occur in the existing SRAM when reading operation

Method used

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  • Storage unit for static random access memory and static random access memory
  • Storage unit for static random access memory and static random access memory

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Embodiment Construction

[0025] The storage unit for the SRAM and the SRAM proposed by the present invention will be further described in detail below in conjunction with the drawings and specific embodiments. Advantages and features of the present invention will be apparent from the following description and claims. It should be noted that all the drawings are in a very simplified form and use imprecise scales, and are only used to facilitate and clearly assist the purpose of illustrating the embodiments of the present invention.

[0026] Please refer to figure 2 , which is a schematic structural diagram of a storage unit of the SRAM according to an embodiment of the present invention. Such as figure 2 As shown, the storage unit 20 for SRAM includes: a first NMOS transistor N1, a second NMOS transistor N2, a third NMOS transistor N3, a first PMOS transistor P1, a second PMOS transistor P2 and a third PMOS transistor P3; the first NMOS transistor N1 and the first PMOS transistor P1 form a first i...

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Abstract

The invention provides a storage unit for a static random access memory and the static random access memory, wherein the storage unit for the static random access memory comprises a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a first PMOS transistor, a second PMOS transistor and a third PMOS transistor; a first inverter is composed of the first NMOS transistor and the first PMOS transistor; a second inverter is composed of the second NMOS transistor and the second PMOS transistor, the first inverter and the second inverter are in cross coupling to form a bistable trigger; the third NMOS transistor is connected with the output end of the first inverter, and the third PMOS transistor is connected with the output end of the second inverter. In the storage unit for the static random access memory and the static random access memory, the three NMOS transistors and the three PMOS transistors are adopted, so that reading and writing are independent with each other, the redundancy degree of reading and writing is increased, and thus the stability of a reading state of the static random access memory is improved.

Description

technical field [0001] The invention relates to the technical field of memory, in particular to a storage unit for a static random access memory and the static random access memory. Background technique [0002] With the development of storage technology, various types of semiconductor memories have emerged, such as static random access memory (SRAM), dynamic random access memory (DRAM), erasable programmable read-only memory (EPROM), electrically erasable programmable Read memory (EEPROM) and flash memory (Flash), etc. [0003] Among them, SRAM does not use capacitors, but stores data based on bistable flip-flops, so the stored data can be saved without periodically charging the capacitors. As long as there is continuous power supply, the SRAM can maintain its storage state without any data updating operation. Since it can operate normally without constant charging, the processing speed of the SRAM is faster and more stable than other memories, and it is usually used as a...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G11C11/419
Inventor 仲纪者
Owner SEMICON MFG INT (SHANGHAI) CORP
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