Manufacture method of CMOS (Complementary Metal Oxide Semiconductor) image sensor

Abstract

The invention relates to a manufacture method of a CMOS (Complementary Metal Oxide Semiconductor) image sensor. The method comprises the following steps of: providing a pixel unit territory comprising a photodiode active region, a transistor active region and a transistor gate region; carrying out manual optical proximity correction on the transistor gate region of the territory to obtain a pixel unit territory subjected to the correction of the gate region; optimizing the original territory according to the pixel unit territory subjected to the correction of the gate region, wherein the area of the photodiode active region of the optimized pixel unit territory is larger than that of the photodiode active region of the pixel unit territory; and preparing a pixel unit according to the optimized pixel unit territory. The prepared CMOS image sensor meets the requirement for technological parameters of devices, has high fill factor and effectively improves the image quality of the CMOS image sensor.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to a method for manufacturing a CMOS image sensor. Background technique [0002] At present, the charge coupled device (CCD) is the main practical solid-state image sensing device, which has the advantages of low read noise, large dynamic range, and high response sensitivity. The disadvantage of Complementary-Metal-Oxide-Semiconductor (CMOS) technology compatibility is that it is difficult to achieve single-chip integration for image sensors based on charge-coupled devices. The CMOS image sensor (CMOS ImageSensor, CIS) can integrate the pixel array and peripheral circuits on the same chip because of the same CMOS technology. Compared with the charge-coupled device, the CMOS image sensor has small size, light weight, low power Low cost, convenient programming, easy control and low average cost. [0003] A CMOS image sensor includes an array of pixel units, and each pixel ...

AI Technical Summary

Problems solved by technology

resulting in an effective gate region width W eff less than the actual gate width W total , and the advanced optical proximity calibration correction requires multiple feedback experiments and is expensive, so it is generally only applied to the 90nm and below line width process.

Therefore, in the layout design of the pixel unit, considering the limitations of the semiconductor process, in order to prevent the fabricated pixel unit from failing, the width of the gate region will be appropriately relaxed to meet the effective gate region width W eff practical requirements, which actually limits the area of ​​the active region of the photodiode

Images