High-speed image compression VLSI coding method based on systolic array, and encoder

A pulsating array, high-speed image technology, applied in image communication, TV, electrical components, etc., to achieve the effect of simple interface, low resource occupation, and high image quality

Inactive Publication Date: 2010-10-20
INST OF OPTICS & ELECTRONICS - CHINESE ACAD OF SCI
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AI Technical Summary

Problems solved by technology

[0005] The technology of the present invention solves the problem: it overcomes the speed limitation that the general processor, programmable DSP and common image compression chip are difficult to realize the real-time compression of high frame rate and high resolution image, and provides a high-speed image compression VLSI coding

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  • High-speed image compression VLSI coding method based on systolic array, and encoder
  • High-speed image compression VLSI coding method based on systolic array, and encoder
  • High-speed image compression VLSI coding method based on systolic array, and encoder

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Embodiment Construction

[0052] Such as figure 1 As shown, the present invention relates to a high-speed image compression encoder based on a systolic array design. As an embeddable high-speed image compression IP core, it receives the original image data of the camera during use, and writes these data into subsequent recording equipment after compression , because this encoder can achieve real-time data compression of more than 10 times under the premise of ensuring better image quality for high-speed images, it can effectively prolong the recording time of recording equipment and reduce transmission bandwidth.

[0053] The basic flow chart of the algorithm based on the present invention is as follows: figure 2 As shown, it includes 3-level 5 / 3 wavelet transform, optimal quantization, adaptive zero-run coding (AZRL), and Exp-Golomb coding with k=0.

[0054] According to information theory, the amount of information H(x) of a source depends on the distribution probability P(x) of its source symbols,...

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Abstract

The invention relates to a high-speed image compression VLSI coding method based on systolic array, and an encoder. The encoder comprises an image-level controller, a code block level controller, an image segmentation partitioning device, a first, a second and a third level two-dimensional small wave converters, a QRG combined encoder and a code stream packer; the method comprises the steps of: first, using the image segmentation partitioning device to segment the image into code blocks with the size of 32*32; respectively using the first, the second and third level two-dimensional small wave converters for carrying out three-level small wave conversion on the image, then using the QRG combined encoder to read the three-level small wave conversion coefficient, carrying out best quantization, self-adaptive zero run length encoding and Exp-Golomb encoding with k=0, and obtaining code stream; and finally, using the code stream packer to pack the code stream of each code block into file according to the preset format for outputting. The invention greatly accelerates the image compression speed, effectively prolongs the recording time, and improving the transmission capability.

Description

technical field [0001] The invention relates to a high-speed image compression encoding method and encoder based on a systolic array, in particular to a high-speed image compression encoding method and an encoder designed based on wavelet transform and systolic array technology and oriented to VLSI hardware implementation. Background technique [0002] Image information has the characteristics of large amount of information and large amount of data. According to analysis, among the information received by human beings, 20% is received through sound, while the information received through eyes exceeds 80%. It’s better to see at once”, which vividly illustrates the importance and urgency of image information exchange. However, digital images are more than two-dimensional data, and as the size increases, the amount of data increases at a geometric rate. If the contradiction between the huge amount of data and the limited recording space and transmission bandwidth cannot be res...

Claims

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Application Information

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IPC IPC(8): H04N7/26H04N19/63
Inventor 徐智勇徐勇张启衡张耀
Owner INST OF OPTICS & ELECTRONICS - CHINESE ACAD OF SCI
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