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Semiconductor substrate, method for producing semiconductor substrate, and electronic device

A semiconductor and substrate technology, which is applied in the fields of semiconductor devices, semiconductor/solid-state device manufacturing, electrical components, etc., and can solve the problems of rising device costs, high prices, and the use of devices.

Inactive Publication Date: 2010-11-24
SUMITOMO CHEM CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, a GaAs substrate, such as a GaAs substrate or a Ge substrate, which is lattice-matched to GaAs is expensive, which increases the cost of the device.
In addition, the heat dissipation characteristics of these substrates are insufficient, and in order to have a heat dissipation design, it is sometimes necessary to suppress the formation density of devices.
Or there are restrictions to use the device within the range possible for thermal management, etc.

Method used

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  • Semiconductor substrate, method for producing semiconductor substrate, and electronic device
  • Semiconductor substrate, method for producing semiconductor substrate, and electronic device
  • Semiconductor substrate, method for producing semiconductor substrate, and electronic device

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0175] A semiconductor substrate having a Si wafer 102, a barrier layer 104, a Ge layer 120, and an element formation layer 124 was produced, and the relationship between the growth rate of the crystal grown inside the opening formed in the barrier layer 104, the size of the covered area, and the size of the opening was examined. relationship between. The experiment was as follows: the film thickness of the element formation layer 124 grown over a certain period of time was measured while changing the planar shape of the covered region formed on the barrier layer 104 and the shape of the bottom surface of the opening.

[0176] First, covering regions and openings were formed on the surface of the Si wafer 102 in the following steps. As an example of the Si wafer 102, a commercially available single crystal Si substrate was used. SiO as an example of the barrier layer 104 is formed on the surface of the Si wafer 102 by thermal oxidation. 2 layer.

[0177] For the above SiO ...

Embodiment 2

[0190] The length of one side of the coverage area is set to 200 μm, 500 μm, 700 μm, 1000 μm, 1500 μm, 2000 μm, 3000 μm, or 4250 μm. For each case, a semiconductor substrate was produced in the same procedure as in Example 1, and the film thickness of the element formation layer 124 formed inside the opening was measured. In this embodiment, by disposing a plurality of SiO of the same size on the Si wafer 102 2 layer to form the SiO 2 layer. At the same time, the above multiple SiO 2 layers are separated from each other to form the SiO 2 layer. The shape of the bottom surface of the opening was the same as in Example 1. Experiments were carried out in three cases: a square with a side length of 10 μm, a square with a side length of 20 μm, and a rectangle with a short side of 30 μm and a long side of 40 μm. The growth conditions of the Ge layer 120 and the element formation layer 124 were set to the same conditions as in the first embodiment.

Embodiment 3

[0192] The film thickness of the element formation layer 124 formed inside the opening was measured in the same manner as in Example 2, except that the supply amount of trimethylgallium was halved and the growth rate of the element formation layer 124 was reduced by about half. It should be noted that in Example 3, the length of one side of the covered region was set to 200 μm, 500 μm, 1000 μm, 2000 μm, 3000 μm or 4250 μm, and the experiment was carried out in the case where the bottom shape of the opening was a square with a side length of 10 μm.

[0193] exist Figure 28 , Figure 29 ~ Figure 33 , Figure 34 ~ Figure 38 And Table 1 shows the experimental results of Example 2 and Example 3. Figure 28 The average value of the film thickness of the element formation layer 124 in each case in Example 2 is shown. Figure 29 ~ Figure 33 Electron micrographs of the element formation layer 124 in each case of Example 2 are shown. Figure 34 ~ Figure 38 Electron micrographs of t...

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Abstract

A high-quality GaAs crystal thin film is obtained by using a low-cost Si substrate having excellent heat dissipation characteristics. Specifically disclosed is a semiconductor substrate comprising an Si substrate, an inhibition layer formed on the substrate and inhibiting crystal growth, in which inhibition layer there are a covering region covering a part of the substrate and an opening region formed within the covering region and not covering the substrate, a Ge layer crystal-grwon in the opening region, a buffer layer crystal-grown on the Ge layer and composed of a P-containing group 3-5 compound semiconductor layer, and a functional layer crystal-grown on the buffer layer. In the semiconductor substrate, the Ge layer may be formed by annealing which is performed at such a temperature for such a time that crystal defects can move.

Description

【Technical field】 [0001] The present invention relates to a semiconductor substrate, a method for manufacturing the semiconductor substrate, and an electronic device. In particular, the present invention relates to a semiconductor substrate in which a crystalline thin film having excellent crystallinity is formed on an inexpensive silicon substrate, a method for manufacturing the semiconductor substrate, and an electronic device. 【Background technique】 [0002] In GaAs-based and other compound semiconductor devices, various high-function electronic devices are developed using heterojunctions. On the other hand, for high-performance electronic devices, since the quality of the crystallinity will affect the characteristics of the device, a crystal thin film with good quality is sought. In the thin film crystal growth of GaAs-based devices, GaAs or Ge whose lattice constant is very close to GaAs is selected as the substrate according to the requirements such as lattice matchin...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/20H01L21/331H01L29/737
CPCH01L21/0245H01L21/02546H01L21/02639H01L21/02463H01L29/045H01L21/02433H01L21/0262H01L29/66242H01L21/02516H01L29/7371H01L29/205H01L21/02381
Inventor 高田朋幸山中贞则秦雅彦
Owner SUMITOMO CHEM CO LTD