Nonvolatile storage gate and its operating method, and logic circuit incorporating nonvolatile storage gate and its operating method

一种非易失性存储、易失性存储的技术，应用在逻辑电路、具有逻辑功能的逻辑电路、信息存储等方向，能够解决需要时间、数据乱码、存储门电源供给不稳定等问题，达到削减漏电流的效果

Active Publication Date: 2011-01-26
ROHM CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] In addition, when the power supply of the logic operation unit is turned on, the power supply of the memory gate is likely to be unstable, and it is necessary to deal with data garbled codes (data け) Countermeasures
In the case of saving all the data in the memory gate to the outside before turning off the power, cutting off the power supply of the memory element does not require the above measures, but there is a problem that it takes time to save the data when the amount of data to be saved is large.
In addition, when the power supply of the logic operation unit is turned on, the power supply to the memory gate is likely to be unstable, and countermeasures against data garbled characters are also required.
[0009] If all the data in the memory gate is saved before the power is turned off, the memory element is also powered off, so the above-mentioned countermeasure is unnecessary, but there is a problem that it takes time to save the data when the amount of data to be saved is large.

Method used

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  • Nonvolatile storage gate and its operating method, and logic circuit incorporating nonvolatile storage gate and its operating method
  • Nonvolatile storage gate and its operating method, and logic circuit incorporating nonvolatile storage gate and its operating method
  • Nonvolatile storage gate and its operating method, and logic circuit incorporating nonvolatile storage gate and its operating method

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no. 1 approach 〕

[0149] (non-volatile CPU)

[0150] Such as figure 1 As shown, the non-volatile CPU 1 according to the first embodiment of the present invention includes: a command processing unit 102; a calculation processing unit 110, which is connected to the command processing unit 102 and receives the calculation control signal ACS from the command processing unit 102; a calculation result storage unit 104, which is connected to the calculation processing unit 110, and receives the calculation output signal z from the calculation processing unit 110; the switch part 106, which is connected to the calculation result storage unit 104 and the command processing unit 102, and supplies the output signal a to the calculation processing unit 110; The switch unit 108 is connected to the switch unit 106 and the command processing unit 102 , receives the switch control signal SCS from the command processing unit 102 , and supplies the output signal b to the arithmetic processing unit 110 .

[0151...

no. 2 approach

[0318] This implementation is in figure 1 In the illustrated nonvolatile CPU 1 , a nonvolatile memory gate 212 described below is applied instead of the nonvolatile memory gate 12 . Except for the point described below, the rest is the same as that of the first embodiment, and thus description thereof will be omitted.

[0319] (Example of configuration of nonvolatile memory gate 212)

[0320] Such as Figure 17 As shown, the nonvolatile memory gate 212 applicable to the nonvolatile memory gate built-in logic circuit of this embodiment includes: a volatile memory unit 224 including data holding circuits 133a, 133b, an inverter circuits 170 , 178 , and transfer gates 146 , 172 ; and a nonvolatile storage unit 218 having a ferroelectric capacitor 51 .

[0321] The data holding circuit 133b holds data by connecting the inverter circuits 136 and 138 in series in a loop at the time of data lock. The inverter circuit 136 is arranged on the main signal path, and the inverter circu...

no. 3 approach

[0385] This implementation is in figure 1 In the illustrated nonvolatile CPU 1 , a nonvolatile memory gate 412 described below is applied instead of the nonvolatile memory gate 12 . Except for the point described below, the rest is the same as that of the first embodiment, and thus description thereof will be omitted.

[0386] (Example of configuration of nonvolatile memory gate 412)

[0387] Such as Figure 22 As shown, the nonvolatile storage gate 412 applicable to the nonvolatile storage gate built-in logic circuit of this embodiment includes: a nonvolatile storage unit 418; a volatile storage unit 424, which receives data input Signal D, clock signal CK, output data output signal Q.

[0388] In the nonvolatile storage gate 412, the data interface control unit described in the above-mentioned embodiment is not shown as a circuit element, but the cell plate potential CP input to the nonvolatile storage unit 418 corresponds to the nonvolatile gate potential CP of the above...

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Abstract

Provided is a logic circuit incorporating a nonvolatile storage gate which can hold data even after turning off the power supply, wherein the power supply can be turned off simultaneously upon entering a standby mode. A logic circuit (10) incorporating a nonvolatile storage gate comprises a logical operation section (14) having a logic gate (16), and a nonvolatile storage gate (12) having a nonvolatile storage section (18), a data interface control section (22) disposed contiguously to the nonvolatile storage section (18) and adapted for receiving a nonvolatile storage control signal (NVCTL) for writing data in the nonvolatile storage section (18) and reading data therefrom, and a volatile storage section (24) disposed contiguously to the nonvolatile storage section (18), and adapted for receiving a data input signal (D) and a clock signal (CLK) and outputting a data output signal (Q).

Description

technical field [0001] The present invention relates to a non-volatile memory gate and its operation method, and a non-volatile memory gate built-in logic circuit and its operation method, in particular to a non-volatile memory gate using a non-volatile memory element and its operation Method, nonvolatile storage gate built-in logic circuit and its operating method. Background technique [0002] In a large scale integrated circuit (LSI: Large Scale Integration) such as a central processing unit (CPU: Central Processing Unit), power is normally consumed due to leakage current even when the LSI is not operating. It is particularly remarkable in recent microprocessors. In 90nm processors, it accounts for 30% of the total power consumption. [0003] What is effective in reducing the leakage current is the method of turning off the power supply in the state (standby state) where the LSI is not performing arithmetic processing. However, when the power is cut off, the processed d...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03K19/00
CPCH03K19/20G11C11/22H03K3/0375
Inventor 木村启明渊上贵昭藤森敬和
Owner ROHM CO LTD
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