Method and system for recovering data clock

Abstract

The invention discloses a method for recovering a data clock, which comprises the following steps of: taking an effective indication signal of client layer data as a write enabling signal of a time slot gap uniformization first in first out (FIFO) register; generating a read enabling signal of the time slot gap uniformization FIFO register; according to the write enabling signal and the read enabling signal, when reading and writing the time slot gap uniformization FIFO register, sampling address differences of a reading pointer and a writing pointer; judging whether the gap time slot of the read enabling signal needs to be regulated according to the address differences, if so, regulating the gap time slot of the read enabling signal to ensure that a sampling value of the address differences of the reading pointer and the writing pointer of the time slot gap uniformization FIFO register is in a threshold value range; and performing counting and frequency division on the read enabling signal to generate a reference clock, and recovering the reference clock into a client layer clock signal. The method can overcome the defects of high system cost, large complexity and poor system stability in the prior art.

Description

technical field [0001] The invention relates to the technical field of optical transmission, in particular to a data clock recovery method and system. Background technique [0002] In transmission technology, asynchronous mapping or asynchronous multiplexing is often used to map low-rate client layer signals into high-rate service layer signals. For example, mapping PDH (Pseudo-Synchronous Digital Hierarchy) signals into SDH (Synchronous Digital Hierarchy) signals, multiplexing low-order ODUk (Optical Channel Data Unit) signals into high-order ODUk; and mapping ODUk signals into STM-N (Synchronous data module) to map STM-N signals into ODUk, etc. Take the mapping of ODU2 to C4-68c as an example: [0003] The structure of C4-68c is: 9 rows×17680 columns. Write the ODU2 data into the FIFO memory according to the clock of the ODU2, insert the fixed filling byte R, the adjustment control byte J and the negative adjustment opportunity byte S on the read side according to the F...

AI Technical Summary

Problems solved by technology

[0006] The clock recovery device must smooth two clock gaps: 1. Fixed ratio gaps in mapping or multiplexing structures

2. Random gaps introduced by positive and negative adjustment bytes

However, due to the lack of monitoring of the data in the demapping or demultiplexing FIFO in this method, when positive and negative data accumulation occurs in the demapping or demultiplexing FIFO, the demapping or demultiplexing FIFO cannot be compensated

This will cause the risk of demapping or demultiplexing FIFO overflow or read empty, thus affecting the stability of the system

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