SSRAM access control system

Abstract

The embodiment of the invention provides a synchronous static random access memory (SSRAM) access control system. The system comprises an access control unit and a plurality of ports, wherein one end of each of the plurality of ports is connected with the access control unit, while the other end is connected with external access equipment; the access control unit configures an access right to an SSRAM for each port through a time division arbitration scheme; and each port accesses the SSRAM through the access control unit within the access right. The system can effectively solve the problem of access conflicts of a plurality of external equipment to the SSRAM and improves the utilization rate of SSRAM access at the same time.

Description

Technical field [0001] The present invention relates to the field of wireless communication systems, in particular to a SSRAM Synchronized Static Random Access Memory (SSRAM) access control system and an SSRAM access control method. Background technique [0002] In wireless communication systems, it is often necessary to forward the antenna data between the digital intermediate frequency and the digital signal processor (DSPDigital Signal Processor). Because the digital intermediate frequency output antenna data is uniformly and continuously sampled, the digital intermediate frequency output data is relatively slow DSP needs to process these sampling values ​​in the shortest possible time. The reading is burst and is completed instantly. Therefore, the reading speed of DSP is very fast, so there is a huge difference in the speed of data transmission between the two parts. , Resulting in the inconsistency of device read and write access and low data transmission efficiency during ...

AI Technical Summary

Problems solved by technology

[0005] The above two methods can solve the problem of read and write conflicts caused by multiple devices accessing a memory at the same time, but the disadvantages are also very obvious.

Increase the number of memories, and the number of pins connected to the corresponding memory and FPGA will also double. Taking SSRAM as an example, the number of pins of 4 pieces of SSRAM reaches about 400, which is the same as the number of user IOs of the FPGA connected to it. It also increases, which makes the connection relationship between FPGA and memory more complicated, and the scale of FPGA is too large, and the cost is correspondingly too high; for dual-port RAM, because adding a port will also double the number of pins, so its disadvantage There are also too many pins, about 200, occupying nearly half of the pins of a medium-sized FPGA, the connection relationship is too complicated, and the cost is correspondingly too high

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