Power bus structure used for multi-power supply chip

Abstract

The invention discloses a power bus structure used for a multi-power supply chip, which comprises a group of global power supply bus and a plurality of power supply groups. The global power bus penetrates through the whole chip and is electrically connected with each power supply group, wherein at least one of two adjacent power supply groups has a local power bus, each power supply group is provided with a plurality of power supply units, at least one power supply unit is provided with an electrostatic discharge device used for separating a high-potential local power supply bus from a low-potential global power supply bus, and at least another power supply unit is provided with an electrostatic discharge device used for separating a low-potential local power supply bus from a high-potential global power supply bus. Under the condition that the chip has more power supply groups, the power bus structure can reduce the area of the chip.

Description

technical field

[0001] The invention relates to semiconductor integrated circuit design, in particular to a power bus structure for multi-power chips. Background technique

[0002] Today's integrated circuit chips generally have multiple sets of power supplies in order to isolate noise. Commonly used power packs are used for input and output (I / O), internal logic circuits, various analog circuit modules, and for testing. For general pure logic chips, two to three sets of power supplies are sufficient. But for digital-analog hybrid (Mixed Signal) chips or system-on-chip (SOC), more than three groups or even as many as a dozen groups of power supplies will be integrated in an independently packaged chip.

[0003] As the number of integrated circuit chip power packs increases, the design of its full-chip electrostatic protection becomes more complicated. At present, the solution of multi-region multi-power bus is generally adopted, and multiple groups of power supplies for d...

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