Forming method of aligned layer graphs on silicon wafer
A technology for aligning layers and silicon wafers, which is applied in the direction of electrical components, semiconductor/solid-state device manufacturing, circuits, etc., and can solve the problems of long manufacturing time and increased process costs
Active Publication Date: 2012-07-11
SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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[0014] The method for forming the pattern of the aligned layer on the silicon wafer requires two photolithography processes, which increases the cost of the process and makes the manufacturing time longer
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[0028] The method for forming the pattern of the aligned layer on the silicon wafer of the present invention comprises the following steps:
[0029] Step 1, see Figure 2a , deposit a layer of first dielectric layer 21 on the silicon substrate or polysilicon 20, the first dielectric layer 21 can be silicon oxide (SiO 2 ), silicon nitride (Si 3 N 4 ), silicon oxynitride (SiO x N y , x and y are natural numbers), etc. A photoresist 22 is then spin-coated on the first dielectric layer 21 , exposed and developed by a photolithography process to form a photolithography pattern, that is, an etching window 23 . If this is the first lithography on the silicon wafer, it is the silicon substrate 20 ; if this is the second or subsequent lithography on the silicon wafer, it is the polysilicon 20 .
[0030] Step 2, see Figure 2b A groove 24 is etched in the etching window 23, the groove 24 penetrates the first dielectric layer 21, the bottom of the groove 24 falls in the silicon su...
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The invention discloses a forming method of aligned layer graphs on a silicon wafer, which comprises: (1) a first dielectric layer is deposited on a silicon substrate, and an etching window is formed through photoetching; (2) a groove is etched in the etching window; (3) a layer of silicon oxide which is firstly deposited on the side wall and at the bottom of the groove is taken as a substrate oxidation layer, a layer of interlamination medium is deposited on the surface of the silicon wafer, and the groove is full of the interlamination medium at least; (4) the interlamination medium is grinded by adopting a chemical and mechanical grinding process; (5) the first dielectric layer is eliminated by adopting a wet method etching process, and a groove is formed on the surface of the silicon wafer again at the position of the original groove; and (6) a layer of polycrystalline silicon is deposited on the surface of the silicon wafer, a second dielectric layer is deposited, and the upper surface of the deposited polycrystalline silicon is provided with a downwards concave step, i.e. the aligned layer graphs. The forming method can be used for saving the manufacturing process and the manufacturing time of the aligned layer graphs, and a photoetching machine can clearly identify the aligned layer graphs on the silicon wafer.
Description
technical field [0001] The invention relates to a manufacturing process of a semiconductor integrated circuit, in particular to a method for forming an aligned layer pattern in a photolithography process. Background technique [0002] Photolithography is a process of transferring the circuit structure in the form of a pattern on a mask to the surface of a silicon wafer coated with photoresist through steps such as alignment, exposure, and development. The photolithography process will form a layer of photoresist mask pattern (photolithography pattern) on the surface of the silicon wafer, and its subsequent process is etching or ion implantation. [0003] The manufacture of any semiconductor device includes a multi-step photolithography process. In addition to the first step of photolithography, the photolithography pattern of the current layer must be overlaid with the aligned layer pattern of the previous layer in each step of photolithography. , to ensure alignment of pat...
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IPC IPC(8): H01L21/00
Inventor 陈福成
Owner SHANGHAI HUAHONG GRACE SEMICON MFG CORP