Control method of system having many inter-integrated circuit (I2C) buses

A control method and bus controller technology, applied in the direction of instrumentation, electrical digital data processing, etc., can solve the problems of multi-CPU resources, inability to realize multi-channel I2C bus, low efficiency, etc., to enhance execution efficiency, eliminate data transmission and processing The effect of the bottleneck

Active Publication Date: 2011-04-20
深圳市研祥慧视科技有限公司
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Problems solved by technology

[0005] The technical problem to be solved in the present invention is, can not realize multi-channel I2C bus for the processing of prior art; After realizing with pure software I2C interface, it will occupy more CPU r

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Example Embodiment

[0044] like figure 1 As shown, in the system with multi-channel I2C bus of the present invention, it mainly includes a processor and a programmable logic device connected with the processor, and the I2C bus of the processor is expanded, so that the processor can have multiple I2C bus channel, each I2C bus can hang multiple different devices, which can be master devices or slave devices. The processor uses the local bus to communicate with the programmable logic device through the address line, data line, read-write signal line and chip select signal line, and executes the control software inside the programmable logic device to complete the communication function with the main body of the processor, and at the same time For processing, complete the complete I2C protocol, complete the function of the I2C bus controller inside the programmable logic device, thereby completing the conversion from the local bus of the processor to the I2C protocol, and use the programmable logic d...

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Abstract

The invention relates to a control method of a system having many inter-integrated circuit (I2C) buses. In the method, a process processes the data communication in many I2C buses in parallel; the processor has two working states for each I2C bus; and the data reception and transmission of the I2C bus controller of each I2C bus are controlled according to the working state of the processor, wherein when the processor is in a main working state, the communication clock of the I2C bus controller of the I2C bus is generated. In the system, by controlling a process to process the I2C buses in parallel, a bottleneck in data transmission and processing is eliminated and the execution efficiency of the system is enhanced. In the embodiment, a programmable logic element is used to expand the main I2C bus of the processor, so that the processor may have many I2C buss channels and each I2C bus can be connected with many sets of equipment, which may be master equipment or slave equipment, for meeting requirements for use on some special occasions, particularly monitoring systems.

Description

technical field [0001] The present invention relates to a system control method, and more particularly, to a control method of a system with multiple I2C buses. Background technique [0002] The I2C bus is a two-wire bus developed by Philips for the connection between IC devices. It is a bidirectional, two-wire, serial, multi-master interface standard. It has a bus arbitration mechanism and is very suitable for close proximity between devices. Distance, infrequent data communication. It transmits data between devices connected to the bus through two lines, SDA (serial data line) and SCL (serial clock line), and identifies each device according to its address. Each device connected to the bus can pass Unique address and simple master-slave relationship that always exists Software sets the address The master can act as a master transmitter or a master receiver. It is a true multi-master bus that prevents data corruption through collision detection and arbitration if two or m...

Claims

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Application Information

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IPC IPC(8): G06F13/40
Inventor 王从毫王玉章
Owner 深圳市研祥慧视科技有限公司
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