Amorphous silicon-based comparator and liquid crystal display
An amorphous silicon and comparator technology, applied in the field of semiconductor integrated circuits, can solve the problems of low carrier mobility, long response time of comparator circuits, poor delay performance, etc., achieve simple process, improve delay performance, and improve The effect of response speed
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Embodiment 1
[0018] figure 1 It is a schematic structural diagram of an amorphous silicon-based comparator provided in the first embodiment of the present invention. The comparator in this embodiment mainly includes three parts, a detection unit 100, a comparison unit 200, and an amplification unit 300. Among them, the detection unit 100 is used to compare the input comparison voltage Vin with the reference voltage Vref, and output the difference between the comparison voltage Vin and the reference voltage Vref; the comparison unit 200 is used to form an intermediate voltage, and the output of the detection unit 100 The difference value and the intermediate voltage are superimposed to output a control voltage; the amplifying unit 300 includes a sixth n-type field effect transistor based on amorphous silicon (hereinafter referred to as T6) and an amplifying circuit 310. T6 is used to conduct or conduct under the control of the control voltage. The amplifying circuit 310 amplifies the voltage ...
Embodiment 2
[0025] image 3 It is a schematic diagram of the structure of an amorphous silicon-based comparator provided by the second embodiment of the present invention. This embodiment can be based on the first embodiment. The specific structure is described as follows:
[0026] In a specific application, the detection unit 100 may adopt various forms of circuits, which can identify the difference between the comparison voltage and the reference voltage. One of the preferred implementations is: the detection unit 100 includes a first n-type field effect transistor (hereinafter referred to as T1) and a second n-type field effect transistor (hereinafter referred to as T2) based on amorphous silicon, and a detection capacitor (hereinafter referred to as T2). C1). The gate of T1 is the first clock input terminal, the gate of T2 is the second clock input terminal; the source of T1 is the reference voltage input terminal, and the source of T2 is the comparison voltage input terminal. The vol...
Embodiment 3
[0035] Figure 4 It is a schematic diagram of the circuit structure of an amorphous silicon-based comparator provided in the third embodiment of the present invention. The difference between this embodiment and the second embodiment is that the structure of the comparison unit 200 is different, and another preferred embodiment is adopted.
[0036] The comparison unit 200 includes T4 and T5 based on amorphous silicon connected in series between the first potential point 203 and the second potential point 204, and the potential of the first potential point 203 is higher than the potential of the second potential point 204. The first connection point between the drain of T4 and the source of T5 forms an intermediate voltage, and as an intermediate output terminal, the gate of T4 is connected to the first potential point 203. T3 is also connected between the first connection point and the second potential point 204, the gate and source of T3 are connected to the first connection poi...
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