On-chip cache structure used for variable memory access mode of general-purpose stream processor

Abstract

The invention discloses an on-chip cache structure used for a variable memory access mode of a general-purpose stream processor, which comprises a memory array unit, a cache controller, a scratch pad memory controller and a memory array boundary segmentation logical unit, wherein the memory array unit comprises a cache part and a scratch pad memory part which are segmented through the memory array boundary segmentation logical unit, the cache controller is used for accessing the cache part in the memory array unit, and the scratch pad memory controller is used for accessing the scratch pad memory part in the memory array unit. The on-chip cache structure has the advantages of simple and compact structure, low cost, good reliability and a wide range of applications, and can change the size ratio of the cache to the scratch pad memory, meet the performances of the processor to the maximum extent and the like.

Description

technical field [0001] The invention mainly relates to the field of cache structure of stream processors, in particular to an on-chip cache structure suitable for variable memory access modes of general stream processors. Background technique [0002] In the latest high-performance microprocessor structure research, stream architecture is becoming a research hotspot, and a variety of processors with stream processing characteristics have emerged, such as the Imagine stream processor designed by Stanford and the STI (Sony, Toshiba, IBM) alliance The launched Cell processor, etc. Streaming architectures can effectively alleviate memory wall bottlenecks, exploit multiple levels of program parallelism, and have been shown to greatly improve processing performance for applications such as media processing and data-intensive scientific computing. Currently mainstream processors and graphics card manufacturers are researching and launching processors with stream processing feature...

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