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Lower hardware mapping method of integrated circuit, and time-space diagram compression method and device

A technology of integrated circuits and space-time maps, which is applied in the fields of electrical digital data processing, special data processing applications, instruments, etc., can solve the problems of time difference of realization, and achieve the effect of convenient and fast realization.

Inactive Publication Date: 2011-05-11
PEKING UNIV SHENZHEN GRADUATE SCHOOL
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

That is to say, the realization of the first part is affected by the technical personnel's own experience and knowledge level, and for different technical personnel, there are large differences in the realization time

Method used

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  • Lower hardware mapping method of integrated circuit, and time-space diagram compression method and device
  • Lower hardware mapping method of integrated circuit, and time-space diagram compression method and device
  • Lower hardware mapping method of integrated circuit, and time-space diagram compression method and device

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Embodiment 1

[0071] In one embodiment of the present invention, a mapping system from computer language to integrated circuit underlying hardware circuits is provided, such as Figure 7 Shown is the integrated circuit lower layer hardware mapping method of the system, including the following steps:

[0072] Step S1, analyze the high-level language program, that is, read the computer language program used to describe the target algorithm of the integrated circuit, and match the mapped execution object and parameter object from the computer language program according to the rules of the computer language. For an ASIC, first design the target algorithm of the integrated circuit according to the function of the integrated circuit, and then write a computer language program describing the algorithm of the integrated circuit. The computer language usually uses C language or MATLAB language. The written computer language program is input into the mapping system of the present invention, and the s...

Embodiment 2

[0098] H.264 is a digital video coding standard jointly formulated by the Joint Video Team (JVT) jointly established by the International Telecommunications Union (ITU-T) and the International Organization for Standardization (ISO). In this embodiment, the X264_me_search function described in the C language of the H.264 standard is taken as an example to describe the step of compressing the space-time graph in Embodiment 1 in more detail.

[0099] Such as Figure 8 The original function of X264_me_search in C language is shown as the operator space-time diagram regenerated by the procedure of program analysis step and data control flow graph generation step mentioned in Embodiment 1, and then through the step of operator structure graph generation step. Since the original program of the X264_me_search function calls the pixel_sad_16×16 function, so in Figure 8 , does not clearly show the specific operator space-time diagram of the called function such as the pixel_sad_16×16 ...

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Abstract

The invention discloses a lower hardware mapping method and device of an integrated circuit. The method comprises the following steps: a program analysis step: reading an analysis program and matching to obtain a mapped execution object and parameter object; a data control flow diagram generation step: mapping the execution object and parameter object to corresponding nodes in the data control flow diagram; an operator time-space diagram generation step: taking out a corresponding operator unit from an operator unit library to expand the data control flow diagram into an operator time-space diagram; a time sequence constraint step: performing time sequence constraint on each layer of the operator time-space diagram according to the total time sequence constraint; and a time-space diagram compression step: performing spatial cluster compression on the time-space diagram according to a time label. The invention also discloses a time-space diagram compression method and device, wherein the method comprises a step of spatially merging and compressing operators with the same operation attribute and / or storage attribute by introducing a control operator. By using the method and device, the design speed of the integrated circuit is increased.

Description

technical field [0001] The invention relates to the field of integrated circuit design, in particular to an integrated circuit lower layer hardware mapping method, a space-time diagram compression method and a device. Background technique [0002] Such as figure 1 As shown, in the prior art, the design of an integrated circuit usually includes two parts: the first part is from the algorithm description based on C language or MATLAB language to the description of the RTL level; the second part is from the RTL level description to the standard cell ASIC structure or Gate array implementation (or other S-ASIC structure) or FPGA structure implementation process. [0003] In the prior art, there are many mature tools that support the realization of the above-mentioned second part, and the realization process basically meets the requirements of high efficiency and quickness; while the realization of the above-mentioned first part is still mainly performed by technicians according...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F17/50
Inventor 王新安胡子一安辉耀王腾谢峥张兴周生明赵秋奇马芝孙亚春
Owner PEKING UNIV SHENZHEN GRADUATE SCHOOL
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