Sampling clock synchronization method for orthogonal frequency division multiplexing (OFDM) system

Abstract

The invention relates to a sampling clock synchronization method for an orthogonal frequency division multiplexing (OFDM) system, which aims at providing the sampling clock synchronization method with the advantages of high precision, simple algorithm and little expense. The method comprises the following steps of: firstly, using two training sequences to estimate sampling clock frequency deviation, then, realizing the sampling rate conversion through the sampling clock frequency deviation information by using a polynomial interpolation filter, correcting the sampling clock frequency deviation, and using few frequency-domain discrete pilot frequencies for correcting the phase deflexion caused by residue sampling clock deviation. When the technical scheme is adopted, the defect of influence on a system caused by the sampling clock frequency deviation can be completely overcome, and the goal of high-precision sampling clock synchronization is reached.

Description

technical field [0001] The invention belongs to the technical field of communication and relates to a synchronization method, in particular to a sampling clock synchronization method in an OFDM system with high-order modulation. Background technique [0002] In an OFDM (Orthogonal Frequency Division Multiplexing) system, since the sampling clocks at both ends of the transceiver are not completely consistent, the resulting sampling frequency deviation may cause the following two problems: on the one hand, the occurrence of subcarriers The phase deflection introduces inter-carrier interference (ICI) at the same time, resulting in the loss of signal-to-noise ratio; on the other hand, it leads to slow symbol timing offset, which makes FFT windowing inaccurate and introduces inter-symbol interference (ISI). However, for OFDM systems with high-order modulation such as 1024QAM, these systems are more sensitive to sampling clock deviations and require high-precision sampling clock s...

AI Technical Summary

Problems solved by technology

[0002] In an OFDM (Orthogonal Frequency Division Multiplexing) system, since the sampling clocks at both ends of the transceiver are not completely consistent, the resulting sampling frequency deviation may cause the following two problems: on the one hand, the occurrence of subcarriers Phase deflection, while introducing inter-carrier interference (ICI), resulting in loss of signal-to-noise ratio; on the other hand, slow symbol timing offset, making FFT windowing inaccurate, and introducing inter-symbol interference (ISI)

Currently widely used OFDM systems usually only reach 64QAM modulation order (such as 802.11a, 802.16, DVB, etc.), so most of the current sampling clock synchronization technologies are aimed at meeting the needs of 64QAM modulation, lacking high-precision sampling clock synchronization algorithm

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