Method for implementing pre-read FIFO and pre-read FIFO

Abstract

The invention provides a method for implementing a pre-read first in first out memory (FIFO) and the pre-read FIFO. The setting of an output register breaks through a key path consisting of output of a random access memory (RAM) and operation of a subsequent user logic unit, the output is completed through a single register, and the output delay is reduced, so that the pre-read FIFO better meets the time sequence requirement. In addition, when an enabling controller determines that the RAM is in a non-idle state and the output register is in an idle state, or when a read request is received, the read signal of an input FIFO controller is valid, and the output register can output data; otherwise, the read signal of an output FIFO controller is invalid, and the output register is latched. In the mode, the enabling controller can still ensure accurate implementation of a pre-read mode on the basis of increasing a primary register.

Description

technical field [0001] The invention relates to memory technology, in particular to a method for realizing a pre-read FIFO and the pre-read FIFO. Background technique [0002] In the field programmable gate array (FPGA) design, the first-in-first-out register (FIFO) is one of the most commonly used functional modules. According to the different requirements for interface timing, FIFO can be divided into pre-read FIFO and non-pre-read FIFO. Two, among them, the read-ahead FIFO can improve the processing efficiency of the subsequent module, so it is often used in high-speed design. [0003] The difference between the pre-read FIFO and the non-pre-read FIFO is mainly: in the pre-read FIFO, if there is data, the data is already prepared on the bus, that is, the data is already valid before the user initiates a read request. After request, the data can be read out in the current clock cycle, while the non-read-ahead FIFO needs to read out the data in the next clock cycle. Among...

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Problems solved by technology

[0005] However, in the above process, the output of the RAM to the subsequent user logic unit is executed within one clock cycle, which obviously has a greater impact on the logic timing of the RAM. Among them, the impact of the delay caused by the output of the RAM is more prominent, especially in For occasions with high timing requirements, such as high clock frequency, high logic utilization rate, or complex combinatorial logic processing in the subsequent stage, the existing pre-read FIFO often cannot meet the timing requirements.

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