Read circuit for EEPROM (Electrically Erasable Programmable Read-Only Memory)

Abstract

The invention discloses a read circuit for an Electrically Erasable Programmable Read-Only Memory (EEPROM), which comprises a memory cell array, a reference memory cell, a row decoding circuit, a column selection transistor, a voltage generating circuit and a current comparison circuit, wherein the newly added reference memory cell is arranged in one column, and is near or in the middle of the memory cell array. The voltage generating circuit is used for outputting equal standard voltage and reference voltage for the read operation of the EEPROM, and respectively supplying the standard voltage and the reference voltage to the memory cell and the reference memory cell. The current comparison circuit is used for comparing standard read current with reference read current with 1 / 2 amplitude for the read operation of the EEPROM, and outputting the storage data of the read memory cell. The read circuit for EEPROM eliminates the influence of parasitic parameter to the read circuit, and improves the stability and the reliability of the EEPROM read operation.

Description

technical field [0001] The invention relates to a non-volatile memory (Non Volatile Memory), in particular to an EEPROM. Background technique [0002] see figure 1 , which is a schematic diagram of an EEPROM memory cell. Generally, each EEPROM memory cell 10 includes a selection transistor 11 and a floating gate tunnel oxide transistor (FLOTOX, FLOating gate Tunnel OXide, sometimes referred to as a floating gate transistor) 12 . The selection transistor 11 is connected to a row selection line 21 and a bit line (Bit Line) 22, and the row selection line 21 is a word line (Word Line). The control gate of the floating gate transistor 20 is connected to the erasing terminal 23 . [0003] see figure 2 The floating gate transistor 12 in the EEPROM memory cell includes a source 121, a drain 122 and two layers of overlapping polysilicon gates 123a, 123b. The lower gate is a floating gate 123a surrounded by silicon dioxide ( figure 2 The middle shaded area) is surrounded, insu...

AI Technical Summary

Problems solved by technology

Due to the difference in circuit structure and layout between the reference current generating circuit and the storage unit, the parasitic parameters on the line, the process deviation and the degree of influence on the power supply voltage are also different, resulting in the reference current not being able to meet all operating conditions. Design requirements, this causes large fluctuations in readout time and even misreadouts in some working conditions

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