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Memory circuit and method for controlling same

A technology of memory circuits and memory arrays, applied in the fields of memory circuits and control memory circuits, can solve problems such as high manufacturing cost and leakage current

Inactive Publication Date: 2013-02-06
FARADAY TECH CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, the SRAM array using the technology of US Patent No. 5,581,500 will have very high manufacturing cost (each column in the SRAM array needs a (VSS+Δ) generator 30), and the (VSS+Δ) generator 30 itself is also There will be leakage current phenomenon

Method used

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  • Memory circuit and method for controlling same
  • Memory circuit and method for controlling same
  • Memory circuit and method for controlling same

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Embodiment Construction

[0021] Please refer to Figure 4 , Figure 4 It is a schematic diagram of a memory circuit 400 according to an embodiment of the present invention. like Figure 4 As shown, the memory circuit 400 includes memory arrays 410, 420, and a switch module 430, wherein the memory array 410 has a first terminal N1, a second terminal N2, and the memory array 420 has a third terminal N3, a first Four terminals N4, the switch module 430 includes three switches SW1, SW2, SW3. In addition, the terminal N1 is coupled to the supply voltage Vcc, the terminal N4 is coupled to the supply voltage GND, the switch SW1 is coupled between the terminal N2 and the supply voltage GND, the switch SW2 is coupled between the terminal N2 and the terminal N3, and the switch SW3 It is coupled between the terminal N3 and the supply voltage Vcc. In addition, in this embodiment, the memory arrays 410, 420 are SRAM arrays, that is, the memory arrays 410, 420 respectively include a plurality of SRAM cells, whe...

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Abstract

The invention discloses a memory circuit. The memory circuit comprises a first memory array, a second memory array and a switch module, wherein the first memory array is provided with a first end point and a second end point; the second memory array is provided with a third end point and a fourth end point; the first end point is coupled to a first supply voltage; the fourth end point is coupled to a second supply voltage which is less than the first supply voltage; and the switch module is coupled to the second end point, the third end point, the first supply voltage and the second supply voltage. When the memory circuit is operated in a non-operation mode, the second end point is electrically connected to the third end point by the switch module, the second end point is electrically insulated from the second supply voltage, and the third end point is electrically insulated from the first supply voltage.

Description

technical field [0001] The invention relates to a memory circuit, in particular to a memory circuit capable of reducing leakage current and a method for controlling the memory circuit. Background technique [0002] Please refer to figure 1 , figure 1 It is a schematic diagram of a known static random access memory (Static Random Access Memory, SRAM) unit 100 . like figure 1 As shown, the SRAM unit 100 includes six transistors N1-N4 and P1-P2, and the SRAM unit 100 can switch word line WL, bit line BL and complementary bit line Data access is performed at a voltage level. In addition, because those skilled in the art should understand the operation of accessing the SRAM cell 100 , relevant details are not repeated here. [0003] refer to figure 1 , when the SRAM unit 100 is in the non-operation mode (that is, the transistors N3 and N4 are in a non-conductive state), the voltage levels of the nodes A and B will change due to the leakage current, which will affect the rea...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G11C11/413G11C11/4096
Inventor 李鸿瑜王勇郑坚斌马亚奇李坤地陈家政
Owner FARADAY TECH CORP