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Method for encapsulating low-cost chip fan-out structures

A packaging method and chip technology, which are applied in the manufacturing of electrical components, electrical solid-state devices, semiconductor/solid-state devices, etc., to achieve the effect of realizing large-scale production, reducing process difficulty and process cost

Active Publication Date: 2012-06-13
JIANGYIN CHANGDIAN ADVANCED PACKAGING CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0008] The purpose of the present invention is to overcome the deficiency of the high-cost process of the existing wafer-level fan-out structure packaging method, and realize a low-cost chip fan-out structure packaging method without photolithography process

Method used

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  • Method for encapsulating low-cost chip fan-out structures
  • Method for encapsulating low-cost chip fan-out structures
  • Method for encapsulating low-cost chip fan-out structures

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Embodiment Construction

[0030] see Figure 1~Figure 11 , Figure 1~Figure 11 It is an embodiment diagram of each process of the packaging method of the low-cost chip fan-out structure without photolithography according to the present invention. Depend on Figure 1~Figure 11 It can be seen that the packaging method of the low-cost chip fan-out structure of the present invention includes the following process steps:

[0031] Step 1, take the carrier substrate 2-1, such as figure 1 ;

[0032] Step 2. Pre-form an alignment pattern on the carrier substrate 2-1. The size of the carrier substrate matches the loading capacity of the existing flip-chip machine, usually 250X80, 210x70mm; paste a temporary Adhesive film 2-2, the temporary adhesive film should have double-sided adhesive properties and be able to withstand a certain process temperature, such as figure 2 ;

[0033] Step 3. Flip-chip single or multiple chips 2-3-1 / 2-3-2 onto the carrier substrate with a temporary adhesive film, and fix it ...

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Abstract

The invention relates to a method for encapsulating low-cost chip fan-out structures. The method comprises the following processing steps of: firstly, obtaining a carrier substrate; secondly, adhering a temporary adhesive membrane on the carrier substrate; thirdly, inversely installing a chip on the carrier substrate; fourthly, wrapping and sealing the carrier substrate provided with the chip through a plastic-sealed body so as to form a reconstructed substrate; fifthly, stripping the reconstructed substrate from the carrier substrate; sixthly, covering the reconstructed substrate with a maskplate, and forming a mask figure opening on the mask plate through the photoetching or laser mode; seventhly, forming rewiring metal on the reconstructed substrate, on which the mask figure opening is formed; eighthly, removing the mask plate; ninthly, printing or adhering a protective film for the rewiring metal on the reconstructed substrate; tenthly, forming an opening pattern on the protective film for the rewiring metal; and eleventhly, carrying out ball mounting at the opening pattern and realizing backflow so as to form a metal salient point. The method for encapsulating the low-cost chip fan-out structures can greatly reduce the difficulty and cost of the process, and can realize the volume production of the low-cost chip fan-out structures.

Description

technical field [0001] The invention relates to a packaging method of a low-cost chip fan-out structure. It belongs to the technical field of packaging of integrated circuits or discrete devices. Background technique [0002] In recent years, with the rapid development of electronic packaging technology, some new packaging forms have emerged, especially the emergence of wafer-level packaging, which provides an excellent solution for low-cost packaging. However, the pursuit of product production cost and performance is infinite. The traditional wafer-level packaging technology uses a fan-in structure (Fan-in), which requires that the chip area and packaging area need to maintain a ratio of 1:1. The packaging area is increased, but in turn, the chip area is increased, which in turn increases the chip manufacturing cost. Therefore, with the increasing maturity of wafer-level packaging technology, people have begun to devote themselves to using small chips to complete a packag...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/50H01L21/60H01L21/56
CPCH01L24/19H01L21/568H01L24/96H01L2224/12105H01L2224/24137H01L2924/14H01L2224/19H01L2924/00H01L2924/00012
Inventor 张黎赖志明陈栋陈锦辉
Owner JIANGYIN CHANGDIAN ADVANCED PACKAGING CO LTD