Output circuit, data driver and display device
A technology for output circuits and output terminals, which is applied to instruments, static indicators, etc., and can solve problems such as inability to suppress through current, increase in area, and increase in the number of transistors
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Embodiment approach 1
[0166] figure 1It is a figure which shows the structure of the output circuit of 1st Embodiment of this invention. In this embodiment, the output circuit preferably drives a wiring load. Including: a differential amplifier stage 50, receiving the input voltage VI of the input terminal 1 and the output voltage VO of the output terminal 2 through differential; the output amplifier stage 30, receiving the first and second outputs of the differential amplifier stage 50 (node 3 , 4) and push-pull operation and the output voltage VO corresponding to the input voltage VI is formed from the Pch transistor 101 and the Nch transistor 102 output from the output terminal 2; the amplification acceleration circuit 10 detects the potential difference between the input voltage VI and the output voltage VO, Amplification and acceleration are performed according to the potential difference; and a capacitance connection control circuit 20 includes capacitance elements C1 and C2 whose first t...
Embodiment approach 2
[0228] Next, a second embodiment of the present invention will be described. image 3 It is a figure which shows the structure of 2nd Embodiment of this invention. refer to image 3 , in this embodiment, relative to figure 1 The configuration of the switch (output switch) SW9 is provided between the wiring load. The output switch SW9 temporarily disconnects the output terminal 2 and the wiring load when switching between output periods.
[0229] While the output switch SW9 is off, the charge transfer from the output terminal 2 to the wiring load is interrupted. Therefore, by the operation of the amplifier acceleration circuit 10, the output voltage VO does not slow down, but rapidly changes to the vicinity of the input voltage VI. Corresponding to the voltage, the capacitors C1 and C2 are also charged and discharged.
[0230] Capacitors C1 and C2 can drive the wiring load at high speed even if the output switch SW9 is turned on by completing charge and discharge correspon...
Embodiment approach 3
[0250] Next, a third embodiment of the present invention will be described. Figure 5 It is a timing waveform diagram illustrating the third embodiment of the present invention. The constitution of this embodiment and image 3 The structure of the above-mentioned embodiment is the same.
[0251] This embodiment is for Figure 4 The timing control has been deformed. Figure 5 With Figure 4 Similarly, the operation of driving the wiring load connected to the output terminal 2 via the output switch SW9 will be described. image 3 A diagram of the control timing of each switch of the output circuit.
[0252] Such as Figure 5 As shown, in this embodiment, the Figure 4 The period T1 is divided into periods T1a and T1b. During the period T1a, the switches SW1, SW2, SW21, and SW23 are turned on, and the switches SW22, SW24 are turned off. During the periods T1b and T2, the switches SW1, SW2, SW21, and SW23 are turned off. The switches SW22, SW24 are turned on. The output s...
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