High integration level system in package (SIP) structure

Abstract

The invention relates to a high integration level system in a package (SIP) structure. The structure comprises a substrate, at least a group of wiring packaging layers on the substrate, a top inverted packaging layer on the wiring packaging layers and connection balls arranged below the substrate, wherein the wiring packaging layers comprise erected surface-mount layers, material sealing layers and wiring layers which are arranged on the substrate in sequence; the top inverted packaging layer comprises an inverted surface-mount layer, bottom padding material and a material sealing layer which are arranged on the wiring packaging layers in sequence; and electrical interconnection between the adjacent packaging layers or spaced packaging layers is realized via the wiring layers. Compared with the prior art, the structure which the invention requests to protect has the following beneficial effects: the final packaged products having the functions of the whole system instead of the functions of the single chip can be formed; the interference factors among the resistors, inductors and chips in the system are reduced; and besides, the more complex multilayer interconnection structure can be formed and higher integration level wafer SIP can be realized.

Description

technical field [0001] The invention relates to semiconductor technology, in particular to a highly integrated system-in-package structure. Background technique [0002] With the continuous development of integrated circuit technology, electronic products are increasingly developing in the direction of miniaturization, intelligence, high performance and high reliability. The integrated circuit packaging not only directly affects the performance of integrated circuits, electronic modules and even the whole machine, but also restricts the miniaturization, low cost and reliability of the entire electronic system. With the gradual reduction of the size of the integrated circuit chip and the continuous improvement of the integration level, the electronic industry has put forward higher and higher requirements for the integrated circuit packaging technology. [0003] A package substrate is disclosed in Chinese Patent No. CN1747156C. The packaging substrate includes: a substrate,...

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Problems solved by technology

[0004] The final product packaged and manufactured according to the above method has only a single chip function. However, with the trend of semiconductor products becoming thinner and smaller and the demand for product system functions constantly improving, how to further improve the integration of system-in-package has become an urgent need for those skilled in the art. solved problem

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