Method for manufacturing clearance wall of semiconductor apparatus

Abstract

The invention provides a method for manufacturing a clearance wall of a semiconductor apparatus. The method comprises the following steps of: providing a substrate, wherein the surface of the substrate has a grid structure; forming an oxide layer on the substrate and the grid structure; forming a clearance wall material layer on the oxide layer; and etching the oxide layer and the clearance wall material layer by using etching gas containing fluorocarbon and inert gas but not containing oxygen to form the clearance wall, wherein the flow velocity ratio of the fluorocarbon to the inert gas 0.1to 1. By the method, the problem that the thicknesses of the clearance walls in a dense area and a non-dense area are nonuniform can be effectively solved and the electrical property of the apparatusis improved, so that the apparatus operates at a uniform speed in different environments, and then the qualification rate is improved.

Description

technical field [0001] The invention relates to a semiconductor manufacturing process, in particular to a method for manufacturing a semiconductor device spacer. Background technique [0002] At present, with the rapid development of VLSI, the integration of chips is getting higher and higher, and the circuit design size is getting smaller and smaller. Currently, manufacturers have been able to manufacture semiconductor devices with line widths of 32nm or even smaller. [0003] In the manufacturing process of the existing MOS (Metal Oxide Semiconductor) devices, the technology of setting spacers is usually used to help control and define the source region and the drain region of the dopant implanted into the MOS. Figure 1A and Figure 1B A cross-sectional view of a semiconductor device involved in each step in the process of manufacturing a spacer in the prior art. Please refer to Figure 1A Firstly, a substrate 100 is provided, on which a gate structure 110 has been form...

AI Technical Summary

Problems solved by technology

The traditional etching process will pass on this difference, causing the spacer in the dense area after etching to be thinner than the spacer in the non-dense area

The uneven thickness of the spacer will reduce the electrical performance of the device, and make the device run at different speeds in different environments, resulting in a decrease in the yield

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