Delay signal generating circuit

[0017] In order to make the objectives, technical solutions and advantages of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention, but not to limit the present invention.

[0018] The invention provides a delay signal generating circuit, which can output an invalid clock signal to a D flip-flop when the delayed signal is the same as the signal to be delayed. In this case, the D flip-flop will not sample the data signal from the source, thus greatly reducing dynamic power consumption. The delay signal generating circuit provided by the present invention will be described in detail below.

[0019] figure 2 It is a circuit diagram of a delay signal generating circuit 200 according to a preferred embodiment of the present invention. like figure 2 As shown, the delayed signal generation circuit 200 includes D flip-flops 202 , 204 and 206 , a comparison circuit 216 and a clock switch circuit 218 . The data terminal (D terminal) of the D flip-flop 202 is connected to the signal source 210, the data terminal of the D flip-flop 204 is connected to the signal source 212, the data terminal of the D flip-flop 206 is connected to the signal source 214, and the delayed signal is The output terminals (Q terminals) of flip-flops 202, 204 and 206 are output.

[0020] The comparison circuit 216 includes three pairs of input terminals, corresponding to the D flip-flops 202 , 204 and 206 respectively. In each pair of input terminals, the first input terminal is used for connecting the signal source corresponding to the corresponding D flip-flop, and the second input terminal is used for connecting the output terminal (Q terminal) of the D flip-flop. For example, among a pair of input terminals of the comparison circuit 216 corresponding to the D flip-flop 202, the first input terminal is used to connect to the signal source 210 corresponding to the D flip-flop 202, and the second input terminal is used to connect to the output terminal of the D flip-flop 202 ( Q terminal). The output terminal of the comparison circuit 216 is connected to the control terminal of the clock switch circuit 218 .

[0021] The input terminal of the clock switch circuit 218 is connected to the clock source 208, and the output terminal is connected to the clock terminals (CLK terminals) of the D flip-flops 202, 204 and 206, respectively.

[0022] In a specific operation process, the comparison circuit 216 outputs an invalid level when the level of the first input terminal of each pair of input terminals is equal to the level of the second input terminal, otherwise it outputs a valid level. For example, only when the level of the first input terminal and the level of the second input terminal of the three pairs of input terminals of the comparison circuit 216 are equal, the comparison circuit 216 will output an invalid level; otherwise, it will output a valid level.

[0023] The clock switch circuit 218 outputs a clock pulse from the clock source 208 at its output end when its control end is at an active level, and outputs a constant level at its output end when its control end is at an inactive level. In this way, the D flip-flops 202, 204 and 206 will sample the signals from their respective signal sources (eg, the corresponding signal sources 210, 212 and 214) only when the control terminal of the clock switch circuit 218 is at an active level, When the control terminal of the clock switch circuit 218 is at an inactive level, the D flip-flops 202, 204 and 206 do not sample the signals from their respective signal sources, thereby reducing dynamic power consumption. That is to say, when there is a continuous same data signal in the data signals of each signal source, the comparison circuit 216 will output an inactive level, so as to control the clock switch circuit 218 to output a constant level, so that the D flip-flop will not By sampling the signal from the signal source, the power consumption of the delayed signal generating circuit 200 can be reduced.

[0024] In the specific implementation process, the effective level output by the output terminal of the comparison circuit 206 is high level, and the invalid level is low level; or, the effective level output by the output terminal of the comparison circuit 206 is low level, and the invalid level is level is high.

[0025] In a specific implementation process, when the control terminal of the clock switch circuit 218 is at an inactive level, the constant level output by the clock switch circuit 218 may be a constant high level or a constant low level.

[0026] It should be noted that, in a specific implementation process, the delay signal generating circuit 200 may include more D flip-flops (at least one). At the same time, a pair of input terminals corresponding to the number of D flip-flops will be set on the comparison circuit 216 .

[0027] To sum up, the present invention provides such a delay signal generating circuit, which is respectively connected with a clock source for outputting clock pulses and at least one signal source, and the delay signal generating circuit includes a comparison circuit, a clock switch circuit and at least one signal source. At least one D flip-flop corresponding to one signal source, wherein the comparison circuit includes at least a pair of input terminals corresponding to the at least one D flip-flop, and the first input terminal of each pair of input terminals corresponds to the corresponding input terminal of the pair of input terminals. The signal source corresponding to the D flip-flop is connected, the second input terminal is connected to the output terminal of the D flip-flop corresponding to the pair of input terminals, the output terminal of the comparison circuit is connected to the control terminal of the clock switch circuit, and the input terminal of the clock switch circuit is connected It is connected to the clock source, the output terminal is connected to the clock terminal of each D flip-flop, the data terminal of each D flip-flop is connected to the signal source corresponding to the flip-flop, and the comparison circuit is connected to the first input of each pair of input terminals. When the level of the terminal is equal to the level of the second input terminal, it outputs an invalid level, otherwise it outputs a valid level; when the control terminal of the clock switch circuit is at an effective level, it outputs the clock pulse at its output terminal, and outputs the clock pulse at its control terminal. When it is an inactive level, it outputs a constant level at its output.

[0028] In a specific implementation process, the constant level is a constant high level or a constant low level.

[0029] In a specific implementation process, the valid level is a high level, and the invalid level is a low level; or the valid level is a low level, and the invalid level is a high level.

[0030] The above descriptions are only preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent replacements and improvements made within the spirit and principles of the present invention shall be included in the protection of the present invention. within the range.