Delay signal generating circuit

Abstract

The invention relates to a signal delay technology and provides a delay signal generating circuit aiming at the defect of over-high power consumption of the conventional delay signal generating circuit. The delay signal generating circuit comprises a comparison circuit, a clock switching circuit and a D trigger, wherein the comparison circuit comprises input ends, wherein the first input end is connected with a signal source and the second input end is connected with the output end of the D trigger; the output end of the comparison circuit is connected with the control end of the clock switching circuit; the input end of the clock switching circuit is connected with a clock source, and the output end of the clock switching circuit is connected with the clock end of the D trigger; the dataend of the D trigger is connected with the signal source corresponding to the trigger; when levels of the first input end and the second input end of the comparison circuit are equal, invalid level is output; when the level at the control end of the clock switching circuit is valid level, clock pulse is output at the output end of the clock switching circuit; and when the level at the control endof the clock switching circuit is invalid level, constant level is output at the output end of the clock switching circuit. The dynamic power consumption of the delay signal generating circuit can begreatly reduced.

Description

technical field [0001] The present invention relates to signal delay technology, more specifically, to a delayed signal generation circuit. Background technique [0002] Signal delay techniques are used to delay a signal from a signal source by one or more signal periods. [0003] figure 1 is a circuit diagram of a conventional delay signal generating circuit 100. Such as figure 1 As shown, the delay signal generation circuit 100 includes D flip-flops 102, 104 and 106, wherein each clock terminal (CLK terminal) of the D flip-flops 102, 104 and 106 is connected to a clock source 108, and the D flip-flop The data end (D end) of 102 is connected to signal source 110, and the data end of D flip-flop 104 is connected to signal source 112, and the data end of D flip-flop 106 is connected to signal source 114, and delay signal is from each D flip-flop 102,104 And the output terminal (Q terminal) of 106 outputs. [0004] The power consumption of the above-mentioned delay signal...

AI Technical Summary

Problems solved by technology

[0006] The technical problem to be solved by the present invention is to provide a delay signal generati

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