Method for testing time series data of standard unit

A technology of time series data and test method, which is applied in the field of microelectronics, can solve the problems of unexpandable test structure, test data that does not meet the analysis needs, simple test data, etc., and achieve the effect of convenient test vector and IO circuit scan test

Inactive Publication Date: 2011-11-23
NO 771 INST OF NO 9 RES INST CHINA AEROSPACE SCI & TECH
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  • Description
  • Claims
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Problems solved by technology

[0005] The disadvantages of ring vibration and counter test circuits are that the data types obtained by the test are single, the amount of data is small, and the test structure is not s

Method used

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  • Method for testing time series data of standard unit
  • Method for testing time series data of standard unit
  • Method for testing time series data of standard unit

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Embodiment Construction

[0033] The present invention is described in further detail below in conjunction with accompanying drawing:

[0034] The method of the present invention is as attached figure 1 As shown, including the clock self-generation module, test logic circuit, and testability design module.

[0035] Clock self-generation module, including ring oscillator array OSC_ARRAY for clock generation and clock selection circuit MUX for multi-channel clock selection, the structure is as attached figure 2 shown. Among them, the x-channel output OSC_out[1:x] of OSC_ARRAY is respectively connected to the x-input terminals IN_[2:x+1] of the MUX, and the y-channel OSC_sel signal is respectively connected to the y-selection terminals sel[1:y] of the MUX. CLK_IN is connected to the input terminal IN_1 of MUX.

[0036] OSC_ARRAY module structure as attached image 3 As shown in (a), it consists of x ring oscillator logic OSC_TYPE, and outputs x clock signals OSC_out[1:x]. Among them, OSC_TYPE implem...

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Abstract

The invention discloses a method for testing time series data of a standard unit. The method comprises the following steps that: an external clock signal CLK_IN and an external clock selection signal OSC_sel are connected with a clock self-generating module respectively; an output end CLK_out of the clock self-generating module is connected with a clock end LOGIC_clk of a test logic circuit; a test stimulus TEST_in generated by a testability structure design module is connected with the test logic circuit; and the test logic circuit outputs result data TEST_out generated according to the test stimulus TEST_in to the testability structure design module so as to determine the working correctness of the test logic circuit. By the method, the limit working frequency of the circuit is tested by designing a self-generating frequency-modulated clock so as to capture a method of key routes.

Description

Technical field: [0001] The invention belongs to the field of microelectronics and relates to a method for testing time series data in standard cell library design. Background technique: [0002] As the scale of integrated circuit design becomes larger and the division of labor in the design process becomes more and more clear, more and more ultra-large-scale digital and digital-analog mixed circuit designs adopt semi-custom design methods based on cell libraries and IP (Intellectual Property) libraries accomplish. In the circuit design process, the design company first selects the process manufacturer, and selects the process, cell library version and various digital and analog IPs according to the needs. The design company does not need to worry about the functions, performance parameters and parameter accuracy of the cell library and IP library. These are provided and responsible by the process manufacturer, and the designer only calls the timing model and physical model...

Claims

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Application Information

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IPC IPC(8): G06F17/50
Inventor 赵德益裴茹霞张洵颖吴龙胜唐威汪西虎岳红菊宋森
Owner NO 771 INST OF NO 9 RES INST CHINA AEROSPACE SCI & TECH
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