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Chip packaging device and manufacturing method thereof

A technology of chip packaging and manufacturing method, which is applied in semiconductor/solid-state device manufacturing, electrical components, electrical solid-state devices, etc., and can solve the problems of easy-to-wear cutting tools, heat sinks that are not easy to cut and level, and complex methods.

Active Publication Date: 2011-11-23
CHIPMOS TECH INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, the method disclosed in this patent is complicated, and the cutting tool is easy to wear out because the cutting tool needs to cut the metal heat sink during the cutting step.
Furthermore, metal heat sinks are not easy to cut flat, resulting in poor product quality

Method used

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  • Chip packaging device and manufacturing method thereof
  • Chip packaging device and manufacturing method thereof
  • Chip packaging device and manufacturing method thereof

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0015] figure 1 A schematic cross-sectional view of a chip packaging device 1 according to an embodiment of the present invention is shown. refer to figure 1 As shown, the chip packaging device 1 may include a carrier 11, a chip 14, at least one wire 16, an adhesive layer 17, a heat sink 18 and a sealant 19, wherein the chip 14 is arranged on the carrier 11; the adhesive layer 17 is arranged On the chip 14; the heat sink 18 is arranged on the adhesive layer 17; the wire 16 is electrically connected to the chip 14 and the carrier 11 and partly covered by the adhesive layer 17; and the sealing body 19 partially seals the chip 14, the adhesive layer 17 and the heat dissipation The surrounding area of ​​the stacked structure of the heat sink 18 and the surface 24 of the heat sink 18 are exposed.

[0016] Specifically, the carrier 11 may include at least one chip bonding area 25 and at least one electrical contact 12 , wherein the at least one electrical contact 12 is disposed on...

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PUM

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Abstract

The invention discloses a chip packaging device which comprises a carrier provided with a chip junction zone and at least one electric contact, a chip with an active face and a passive face, at least one lead, a bonding layer, a heat-radiating member and a packaging colloid, wherein the chip is arranged on the chip junction region of the carrier in a manner that the passive face faces the carrier. The active face of the chip comprises at least one bonding pad, and the lead is connected with the at least one bonding pad and the at least one electric contact correspondingly. The bonding layer covers the active face of the chip and wraps a part extending on the bonding pad in the lead. The heat-radiating member is fixed on the bonding layer and covers the chip. The packaging colloid is used for sealing the chip, the bonding layer and the circumferential side of the heat-radiating member, and a concave opening is formed on the packaging colloid for exposing the surface of the heat-radiating member.

Description

technical field [0001] The invention relates to a chip packaging device and a manufacturing method thereof. Background technique [0002] Generally speaking, semiconductor packaging refers to covering a semiconductor chip with a package body, and providing electrical contacts outside the package body to connect external devices or circuits, and the Ball Grid Array (BGA) package technology (BGA) package technology) is often used to construct semiconductor dies with high density and high pin count. In a conventional BGA package, the semiconductor die is placed on the circuit substrate, the semiconductor die is bonded to the circuit substrate by wire bonds, and the package wraps the semiconductor die and the wires. Solder balls are formed on the backside of the circuit substrate to electrically connect external devices and semiconductor chips. [0003] When the circuits on the semiconductor die operate, the semiconductor die generates heat. In the traditional BGA package, th...

Claims

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Application Information

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IPC IPC(8): H01L23/34H01L23/31H01L21/50H01L21/56
CPCH01L2224/32225H01L2224/48227H01L2924/15311H01L2224/73265H01L24/73H01L2924/00012H01L2924/00
Inventor 许翰诚叶庭彰
Owner CHIPMOS TECH INC