Silicon-Based Nanoscale Interleaved Memory

Abstract

This application describes an interleaved memory array. The interleaved memory array includes a first array of parallel nanowires of a first material and a second array of parallel nanowires of a second material. The first array and the second array are oriented at an angle to each other. The array also includes a plurality of nanostructured amorphous silicon deposited between the nanowires of the first material and the nanowires of the second material at each intersection of the two arrays. The nanostructures together with the nanowires of the first material and the second material form a resistive memory cell.

Description

technical field [0001] The present invention relates to a solid-state resistive device for memory storage. Background technique [0002] Recently, a lot of attention has been paid to resistive random access memory (RRAM) as a potential candidate for ultra-high density non-volatile information storage. A typical RRAM device includes an insulator layer sandwiched between a pair of electrodes and exhibits an electrical pulse-induced resistive hysteresis switching effect. [0003] By virtue of the binary oxides (e.g., NiO and TiQ 2 Joule heating and electrochemical processes in ) or redox processes for ionic conductors including oxides, chalcogenides, and polymers to form conductive filaments within insulators illustrate resistive switching. Also by TiO 2 and field-induced diffusion of ions in amorphous silicon (a-Si) films illustrate resistive switching. [0004] In the case of a-Si structures, the voltage-induced diffusion of metal ions into the silicon results in the form...

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Problems solved by technology

However, such devices typically have micron-sized filaments, which may prevent them from scaling down to the sub-100nm range

Such devices may also require high forming voltages, which can lead to device damage and limit yield

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