Impulse frequency correction system of serial bus clock and method thereof

A clock pulse and serial bus technology, applied in the field of serial bus clock pulse frequency calibration system, can solve the problems of complex design, inaccurate frequency, high component cost, etc., and achieve the effect of reducing component cost and simplifying system design

Active Publication Date: 2012-02-08
GENESYS LOGIC INC
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

Patent specification published in '154 figure 2 In the disclosed USB device, it is necessary to additionally use a frequency signal source (please refer to the reference clock pulse generation circuit 132 disclosed in FIG. The synthesizer (please refer to a phase-locked loop (PLL) 134 disclosed in FIG. 7 of the '154 patent specification) corrects its operating frequency according to the reference clock signal. However, this design is too complicated and has the problem of high component cost , and use the reference clock pulse generation circuit to generate the frequency signal source to correct its operating frequency. For USB transmission signals, there is still the problem of inaccurate frequency

Method used

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  • Impulse frequency correction system of serial bus clock and method thereof
  • Impulse frequency correction system of serial bus clock and method thereof
  • Impulse frequency correction system of serial bus clock and method thereof

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Embodiment Construction

[0053] Embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings.

[0054] Please refer to image 3, showing a functional block diagram according to a first preferred embodiment of the present invention, which discloses a USB interface signal transmission between a UBS (Universe Serial Bus, USB) host 30 and a USB device 32, wherein the USB device 32 (such as a USB hub (Hub)) is provided with a serial bus clock pulse frequency calibration system 36, according to the USB input signal sent by the aforementioned USB host that the USB device 32 receives, the operating clock pulse frequency of the USB device 32 is integrated A two-stage clock pulse frequency accuracy correction with different control ranges is proposed, including: the first stage frequency accuracy correction is to use the start of frame (SOF) signal in the USB input signal as a cycle signal, as a preliminary reference for coarse tuning (Coarse Tuning) the ...

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Abstract

The invention discloses an impulse frequency correction system of a serial bus clock and a method thereof. A first frequency regulation device, a second frequency regulation device and a third frequency regulation device share one oscillator to correct the accuracy of the multi-stage clock impulse frequency of different frequency regulation ranges, and therefore the optimal frequency accuracy can be obtained. In addition, system design is greatly simplified, and element cost is lowered.

Description

technical field [0001] The present invention relates to a serial bus clock pulse frequency calibration system and its method, in particular to a serial bus clock pulse frequency calibration system and its method, which is used for multi-stage improvement of data transmission between a serial bus host and a device. Clock Frequency Resolution (Clock Frequency Resolution). Background technique [0002] Because the existing types of consumer electronic products such as communication devices (such as mobile phones), image capture devices, storage devices, and Internet access devices are all developing towards high resolution or high image quality or high storage capacity, etc., and thus need to deal with a large number of digital content. In order to facilitate users to quickly transmit a large amount of digital content between the host (Host) and its peripheral devices (Device), most of these consumer electronic products are equipped with a relatively popular high-speed serial ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F1/04
Inventor 李威德杨新德黄文明
Owner GENESYS LOGIC INC
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