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Method for producing semiconductor device

A manufacturing method and semiconductor technology, applied in semiconductor/solid-state device manufacturing, electrical components, circuits, etc., capable of solving problems affecting the performance of semiconductor devices and not being able to completely remove the barrier layer 500

Active Publication Date: 2015-07-22
SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

In the subsequent process of removing the barrier layer 500, due to the barrier of the polysilicon residue 610, the barrier layer 500 cannot be completely removed, which will eventually affect the performance of the semiconductor device.

Method used

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  • Method for producing semiconductor device
  • Method for producing semiconductor device
  • Method for producing semiconductor device

Examples

Experimental program
Comparison scheme
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Embodiment 1

[0039] refer to Figure 7 As shown, the present embodiment provides a method for manufacturing a semiconductor device, including:

[0040] Step S1, providing a semiconductor substrate;

[0041] Step S2, forming a shallow trench isolation structure in the semiconductor substrate, and the shallow trench isolation structure is used to define a dummy active region and an active region;

[0042] Step S3, forming a barrier layer on the semiconductor substrate, the distance between the upper surface of the dummy active region and the upper surface of the barrier layer is a first thickness, and the lateral width of the dummy active region is smaller than the first thickness. 1.4 times the thickness.

[0043] First execute step S1, refer to Figure 8 As shown, a semiconductor substrate 10 is provided.

[0044] Specifically, the semiconductor substrate 10 may be a silicon substrate, a silicon germanium substrate or a silicon-on-insulator structure, or other semiconductor material su...

Embodiment 2

[0064] refer to Figure 15 As shown, this embodiment is used to form a polysilicon gate, which specifically includes the following steps:

[0065] Step S11, providing a semiconductor substrate;

[0066] Step S2, forming a shallow trench isolation structure in the semiconductor substrate, and the shallow trench isolation structure is used to define a dummy active region and an active region;

[0067] Step S13, forming an oxide layer on the semiconductor substrate;

[0068] Step S14, forming a barrier layer on the oxide layer, the distance between the upper surface of the dummy active region and the upper surface of the barrier layer is a first thickness, and the lateral width of the dummy active region is smaller than the first thickness. 1.4 times the thickness;

[0069] Step S15, forming a polysilicon layer on the barrier layer;

[0070] Step S16, forming a via hole on the polysilicon layer corresponding to the active region;

[0071] Step S17, filling the through hole w...

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PUM

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Abstract

The invention relates to a method for producing a semiconductor device. The method comprises the steps of: providing a semiconductor substrate; in the semiconductor substrate, forming a shallow trench isolation structure for defining a fake active area and an active area; and forming a blocking layer on the semiconductor substrate, wherein a distance between the upper surface of the fake active area and the upper surface of the blocking layer is a first thickness, and the transverse width of the fake active area is 1.4 times less than the first thickness. By employing the method provided by the invention, the residue in the blocking layer on the fake active area can be avoided after the removal of a CMP (Corrugated Metal Pipe).

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a method for manufacturing a semiconductor device. Background technique [0002] As semiconductor technology enters the deep sub-micron era, components below 0.18 microns (such as between the active regions of CMOS integrated circuits) are mostly made of shallow trench isolation (STI) for lateral isolation. In the United States with patent number US7112513 More information about shallow trench isolation technology can also be found in the patent. [0003] The shallow trench isolation structure is a device isolation technology, and its specific process includes: forming a silicon nitride layer on a silicon substrate, and forming a through hole in the silicon nitride, and the through hole has and defines active The shape corresponding to the isolation region of the region; using the silicon nitride layer as a mask, etch the silicon substrate to form an isolation trench; dep...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/762H01L21/318
Inventor 顾靖
Owner SHANGHAI HUAHONG GRACE SEMICON MFG CORP