Clock phase alignment and adjustment circuit

Abstract

The invention relates to a clock phase alignment and adjustment circuit, which can be matched with a phase locked loop with an input frequency divider and a feedback frequency divider so that the phase alignment of clock signals can be realized. The circuit comprises an AND gate, a first delayer and an inverter, wherein the input end of the first delayer is used for receiving a peripheral reset signal; the output end of the first delayer is connected to another input end of the AND gate through a first D trigger and a second delayer in turn so that an enabling signal is output to the AND gate; the input end of the inverter is used for receiving the input clock signals; and the output end of the inverter is connected with the first D trigger. According to the circuit disclosed by the invention, uncertainty conditions, such as burrs and the like, can be effectively avoided by controlling the time for transmitting the clock signals to the frequency divider; various output frequency dividers have the same initial state by using synchronous reset of the D trigger; that is to say, the clock signals output by the phase locked loop or the clock signals directly input from outside are primarily identified at the same time; therefore, the rising edges for outputting the clock signals are synchronous.

Description

technical field [0001] The invention relates to an integrated circuit, in particular to a clock phase alignment adjustment circuit. Background technique [0002] Due to the increased demand for system integration and chip implantation, the various IP (network protocols) required for it are also integrated into the chip. For the current integrated circuit system, DDRX (Double Rate Synchronous Dynamic Random Access Memory) The memory control circuit, OCP, AXI and other bus protocols required by MIPS (millions of machine language instructions processed per second) all have their own phase-locked loops to generate the required clock signals, and these clock signals work no matter At any frequency, relative to the phase of the rising edge of the CPU clock signal, there is a strict requirement for a very small phase difference, that is, the rising edge of the CPU clock signal needs to be synchronized with the rising edges of these IPs and the phase difference is extremely small. ...

AI Technical Summary

Problems solved by technology

[0014] In the prior art, U.S. Patent No. 7948260B1 discloses a phase adjustment device and method for a digital clock signal. The phase of each frequency-divided output clock signal, so that the rising edges of all output clock signals are aligned; however, because the clock signal is frequency-divided and the phase is adjusted, it cannot be guaranteed to have a 50% duty cycle, and, This technical solution can only provide phase alignment for circuits with even frequency division, which requires high-demand process support, and at the same time, it also causes defects such as complex circuits.

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