Nonvolatile memory device with 3D memory cell array

Abstract

Disclosed is a nonvolatile memory device which includes a 3D memory cell array having words lines that extend from a lowest memory cell array layer closest to a substrate to a highest memory cell array layer farthest from the substrate, a voltage generator circuit generating first and second voltage signals, and a row selecting circuit that simultaneously applies the first voltage signal to a selected word line and the second voltage signal to an unselected word line. The selected word line and the unselected word line have different resistances, yet the first voltage signal is applied to the selected word line and the second voltage signal is applied to the unselected word line with a same rising slope over a defined period of time.

Description

[0001] Cross References to Related Applications [0002] This application claims the benefit of Korean Patent Application No. 10-2010-0076537 and No. 10-2011-0011609 filed on Aug. 9, 2010 and Feb. 9, 2010, respectively, the contents of which are hereby incorporated by reference in their entirety . technical field [0003] The inventive concept relates generally to semiconductor memory devices, and more particularly, to nonvolatile memory devices. Background technique [0004] Semiconductor memory devices can be broadly classified as volatile or nonvolatile according to their operational properties. Volatile memory devices lose stored data in the absence of external power, and include static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), and the like. Nonvolatile memory devices retain stored data even in the absence of external power. Non-volatile memory devices include read-only memory (ROM), electrically programmable ROM (EPROM), electrically erasable programm...

AI Technical Summary

Problems solved by technology

However, efficiently designing and fabricating three-dimensional memory cell arrays is a difficult task

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