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Method for preventing low yield of wafer edge device

A wafer and yield technology, which is applied in semiconductor/solid-state device manufacturing, electrical components, grinding devices, etc., can solve the problems of poor edge performance and low yield of wafer edge devices, so as to improve grinding uniformity and reduce Grinding removal rate, the effect of improving production yield

Active Publication Date: 2012-03-21
SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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Problems solved by technology

Therefore, it provides a method to prevent excessive grinding of CMP from causing low yield of wafer edge devices, which can improve the problem of poor edge performance in chemical mechanical polishing, and obtain better planarization effect

Method used

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  • Method for preventing low yield of wafer edge device
  • Method for preventing low yield of wafer edge device
  • Method for preventing low yield of wafer edge device

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Embodiment Construction

[0037] In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. However, the present invention can be implemented in many other ways different from those described here, and those skilled in the art can make similar extensions without violating the connotation of the present invention, so the present invention is not limited by the specific embodiments disclosed below.

[0038] In the manufacturing process of semiconductor devices, there are often situations where the yield rate of wafer edge devices is reduced. The inventors have found through analysis that the main reason for the low yield rate of wafer edge devices is that the wafer edge will be excessively ground after the planarization process. In turn, a short circuit occurs, resulting in low yield of wafer edge devices. Detailed description will be given below.

[0039] In the process of forming metal interconnections, photoresist is us...

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Abstract

The invention discloses a method for preventing low yield of a wafer edge device. In a regional medium layer of the wafer edge, the yield is reduced by excessive CMP (chemical mechanical polishing). The method comprises the following steps: forming a material layer to be polished on a semiconductor wafer; and performing CMP on the material layer to be polished, wherein the polishing removal rate of the wafer edge is less than that of the wafer central area. According to the invention, excessive polishing of the wafer edge is avoided, and the production yield of the wafer edge device is improved.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing technology, in particular to a chemical mechanical polishing method. Background technique [0002] The chemical mechanical polishing (CMP) process is a process technology that can provide global and local planarization of silicon wafers. The chemical mechanical polishing process has been widely used in the removal and planarization of interlayer dielectrics, metal layers, such as tungsten plugs, or copper wiring, shallow trench isolation, and has become an important process in semiconductor manufacturing processes. [0003] In the integrated circuit manufacturing process, after the element structure or patterned metal wires are fabricated on the wafer, a layer of dielectric material will be deposited on the substrate first, and then the subsequent metal layer will be deposited. Depending on the function, this layer The dielectric layer used to isolate metal wires and component...

Claims

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Application Information

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IPC IPC(8): B24B37/02H01L21/304
Inventor 李儒兴秦海燕陶仁峰李志国
Owner SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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