Testing system and method for mixed-mode IC (integrated circuit)

An integrated circuit and mixed-mode technology, which is applied in the test system field of mixed-mode integrated circuits, can solve problems such as difficulty in collecting data for analysis, increase in test cost, difficulty in increasing memory size, etc.

Inactive Publication Date: 2012-04-04
SUNPLUS TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, because the internal memory of the logic analyzer (LA) 160 is limited and its memory size is not easy to increase, it is difficult for the logic analyzer (LA) 160 to collect a large amount of data for analysis, and it is also limited by the logic analyzer (LA) 160 price, the cost of testing will increase a lot

Method used

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  • Testing system and method for mixed-mode IC (integrated circuit)
  • Testing system and method for mixed-mode IC (integrated circuit)
  • Testing system and method for mixed-mode IC (integrated circuit)

Examples

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Embodiment Construction

[0026] Figure 4 It is a block diagram of a mixed-mode integrated circuit (mixed-mode IC) test system 400 of the present invention, the mixed-mode integrated circuit test system 400 includes a mixed-mode integrated circuit 410 and an automatic test device 420 .

[0027] The mixed-mode integrated circuit 410 includes an analog-to-digital converter 411 , a phase-locked loop 413 , a timing pin 415 , a FIFO buffer 417 , and a control circuit 419 .

[0028] The analog-to-digital converter 411 receives a test signal and converts the test signal into a digital input data ADO[n-1:0].

[0029] The PLL 413 receives a first external timing signal XI to generate an input timing signal clk_i, wherein the frequency of the input timing signal clk_i may be an integer multiple of the frequency of the first external timing signal XI, for example, the frequency of the input timing signal clk_i The frequency may be 3 times or 4 times the frequency of the first external timing signal XI, or the f...

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Abstract

The invention provides a testing system and a method for a mixed-mode IC (integrated circuit). The testing system comprises an analog-to-digital converter, a phase-locked loop, a timing pin, a first-in first-out buffer and an automatic testing device, wherein the analog-to-digital converter receives a testing signal and converts the testing signal into digital input data, the phase-locked loop receives a first external timing signal to generate an input timing signal, the timing pin is used for receiving a second external timing signal, the first-in first-out buffer is used for writing in the digital input data according to the input timing signal and for reading out data of the first-in first-out buffer according to the second external timing signal, the automatic testing device is used for generating the testing signal, the first external timing signal and the second external timing signal and locking the data of the first-in first-out buffer according to the second external timing signal.

Description

technical field [0001] The invention relates to the technical field of integrated circuit testing, in particular to a testing system and method for mixed-mode integrated circuits. Background technique [0002] With the advancement of integrated circuit technology, the application design of integrated circuits is becoming more and more complex, so integrated circuit testing has become an important part of the integrated circuit manufacturing process. Integrated circuit testing mainly uses automatic testing equipment (Automatic Testing Equipment, ATE), using test programs to simulate various possible use environments and methods of integrated circuits, such as in harsh environments such as high temperature, low temperature, voltage instability, and high or low voltage Under normal use conditions, the integrated circuit under test is placed in this simulated environment to test whether its working state is within the specification range, so as to ensure the quality of the integ...

Claims

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Application Information

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IPC IPC(8): G01R31/303G01R31/28
Inventor 吴俊毅王及德巫秋田
Owner SUNPLUS TECH CO LTD
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