Trench metal oxide semiconductor field-effect transistor and manufacturing method for same

Abstract

The invention discloses a trench metal oxide semiconductor field-effect transistor with ultrahigh cell density and a manufacturing method for the same. A source region and a body region are arranged in different areas of a device respectively so that the dimension of the device can be effectively decreased. Besides, trench metallic oxides of the trench metal oxide semiconductor field-effect transistor are in stripe cell structures, so that cell packing density is further increased, and starting resistance between a drain electrode and a source electrode is reduced.

Description

technical field [0001] The invention relates to a device structure and a manufacturing method of a semiconductor power device. In particular, it relates to an improved device structure and manufacturing method of a metal oxide semiconductor field effect transistor (Metal-Oxide-Semiconductor-Field-Effect-Transistor, MOSFET) with ultra-high unit density. Background technique [0002] As we all know, for trench semiconductor power devices, the two parameters of channel packing density (channel packing density, that is, the width of the trench per unit area) and cell density (cell density) are important for improving the performance and cost per unit area of ​​the device. Therefore, in the prior art, various structures of trench semiconductor power devices have been proposed in order to obtain higher trench packing density and unit density. [0003] Such as figure 1 As shown, U.S. Patent No. 6,737,704 discloses an N-channel MOSFET located on an N+ substrate 100 . An N-type ep...

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Problems solved by technology

and figure 1 compared to, Figure 4 The trench metal oxide semiconductor field effect transistor in the metal oxide semiconductor field effect transistor is lined with a barrier layer 111 below the metal layer 118', however, the various limitations discussed above have not been substantially improved

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