Method for fabricating radio frequency ldmos devices with double metal silicides

Abstract

The invention discloses a radio frequency laterally diffused metal oxide semiconductor (LDMOS) device with thermometal silicide and a manufacturing method. A P-shaped silicon substrate is provided with P-shaped epitaxy. A N-shaped low doped drain region, a P trap and a N-shaped heavy doped drain region are arranged in the P-shaped epitaxy. A N-shaped heavy doped source region and a P-shaped heavy doped lead out region are arranged in the P trap. A drain electrode titanium silicide layer is arranged on the top of the N-shaped heavy doped source region. A source electrode titanium silicide layer is arranged on the top of the P-shaped heavy doped lead out region and the N-shaped heavy doped source region. A grid electrode titanium silicide layer is arranged on the top of a polycrystalline silicon grid electrode. Thickness of the grid electrode titanium silicide layer is larger than thickness of the drain electrode titanium silicide layer and the source electrode titanium silicide layer. Titanium silicide of a grid electrode is thicker, square resistance of the grid electrode is reduced, and normal thickness titanium silicide on a source electrode and a source electrode avoids electricity leakage to caused by junction penetration of source drain and the trap.

Description

technical field [0001] The invention relates to the field of semiconductor integrated circuits, in particular to a method for manufacturing an RFLDMOS thick isolation dielectric layer structure. Background technique [0002] In high-speed RF LDMOS, the gate resistance is an important factor affecting the switching speed of the device. Since this device requires high output power, the total width will be very large, and multiple fingers are required, and the width of a single finger, that is, the gate length, is also very long, which inevitably makes the series resistance large and needs to be reduced. The square resistance of the gate, and the source and drain also need lower resistance. To minimize the gate resistance, a thicker metal silicide thickness is required, but using the same metal silicide on the source and drain will lead to deeper penetration into the monocrystalline silicon layer and penetration of the junction causing leakage. An existing compromise is to st...

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Problems solved by technology

In order to minimize the gate resistance, a thicker metal silicide thickness is required, but using the same metal silicide on the source and drain will cause leakage into the monocrystalline silicon layer and penetrate the junction.

An existing compromise is to stack tungsten-silicon alloy on heavily doped polysilicon as the gate, and use conventional titanium metal silicide to form the source and drain, but the sheet resistance of this structure is still very large

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