245 results about "Titanium silicide" patented technology

A method is described for forming a semiconductor device comprising a bipolar transistor having a base region, an emitter region and a collector region, wherein the base region comprises polycrystalline semiconductor material formed by crystallizing silicon, germanium or silicon germanium in contact with a silicide, germanide or silicide germanide. The emitter region and collector region also may be formed from polycrystalline semiconductor material formed by crystallizing silicon, germanium or silicon germanium in contact with a silicide, germanide or silicide germanide forming metal. The polycrystalline semiconductor material is preferably silicided polysilicon, which is formed in contact with C49 phase titanium silicide.

A method and apparatus for forming an epitaxial titanium silicide film is described. According to the present invention, a monocrystalline silicon substrate is placed in a deposition chamber and heated to a temperature between 710-770 DEG C. A silicon source gas and titanium tetrachloride are then provided into the deposition chamber. The deposition pressure is maintained between 5-10 torr. An epitaxial titanium silicide film is then formed on the substrate from the silicon source gas and the titanium tetrachloride.

Embodiments of the present invention generally relate to an apparatus and method of integration of titanium and titanium nitride layers. One embodiment includes providing one or more cycles of a first set of compounds, providing one or more cycles of a second set of compounds, and providing one or more cycles of a third set of compounds. One cycle of the first set of compounds includes introducing a titanium precursor and a reductant. One cycle of the second set of compounds includes introducing the titanium precursor and a silicon precursor. One cycle of the third set of compounds includes introducing the titanium precursor and a nitrogen precursor. Another embodiment includes depositing a titanium layer utilizing titanium halide. Then, a passivation layer is deposited over the titanium layer utilizing titanium halide. The passivation layer may comprise titanium silicide, titanium silicon nitride, and combinations thereof. Then, a titanium nitride layer is deposited over the passivation layer utilizing titanium halide. Still another embodiment comprises depositing a titanium layer over a surface of a substrate. Then, the titanium layer is treated with a soak with a silicon precursor at a substrate temperature of about 550° C. or less to form a treated titanium layer. Then, a titanium nitride layer is deposited over the treated titanium layer.

The present invention relates to a semiconductor device wherein a dummy gate electrode is fixed to the same electric potential as that of a substrate, the stable operation of an LSI is maintained and the process margin is large, and also to a producing method of the semiconductor device, and the semiconductor device comprises a P-type silicon substrate, a dummy element region unnecessary for the actual LSI operation, which is formed on the P-type silicon substrate, and a dummy gate electrode unnecessary for the actual LSI operation, which is formed on at least a part of the dummy element region through a dummy oxide film, wherein by selectively forming titanium silicide on at least a part of a surface of the dummy element region and the dummy gate electrode, a P.sup.+ -diffusion layer and a P.sup.+ -dummy gate electrode of the dummy element region are short-circuited by titanium silicide.

Methods for fabricating integrated circuits are provided. One method includes forming first and second FET trenches in an interlayer dielectric material on a semiconductor substrate. The first FET trench is partially filled with a first work function metal to define an inner cavity in the first FET trench. The first work function metal is a N-type work function metal or a P-type work function metal. The N-type work function metal is selected from the group consisting of titanium, tantalum, hafnium, ytterbium silicide, erbium silicide, and titanium silicide. The P-type work function metal is selected from the group consisting of cobalt, nickel, and tungsten silicide. The inner cavity and the second FET trench are filled with a second work function metal to form corresponding metal gate structures. The second work function metal is the other of the N-type work function metal or the P-type work function metal.

A method of making a semiconductor device including a MOS transistor provides an insulator formed on a semiconductor substrate and a gate electrode formed on the insulator. Source / drain regions are formed within the substrate on either side of the gate electrode. A layer of titanium is sputtered onto the semiconductor device, and a layer of titanium nitride is direct sputtered over the titanium layer using a titanium nitride target. The device is annealed at a first temperature to form a structure including titanium silicide on the polysilicon electrode, titanium silicide on the surface of the source / drain regions, unreacted titanium over the silicide regions, and titanium nitride over the unreacted metal. The unreacted titanium and titanium nitride are removed from the structure, and the structure is annealed at a higher temperature than the first temperature to form a lower resistivity titanium silicide.

The method is suitable to display. The method includes steps: first forming a grid pole on a base plate; next, forming an insulating layer of grid pole above the grid pole; also forming a buffer layer between the grid pole and the base plate and / or between the grid pole and the insulating layer of grid pole. The buffer layer includes tantalum silicide, tantalum-silico-nitride, titanium silicide, titanium-silico-nitride, tungsten silicide, tungsten-silico-nitride or tungsten- carbide-nitride. Then, a semiconductor layer is formed above the insulating layer of grid pole, and source / drain poles are formed above partial semiconductor layer. The buffer layer covers the said grid pole.

A process for forming a low resistivity titanium silicide layer on the surface of a silicon semiconductor substrate. In the process, an effective amount of a metallic element such as indium, gallium, tin, or lead is implanted or deposited on the surface of the silicon substrate. A titanium layer is deposited on the surface of the silicon substrate, and a rapid thermal annealing of the titanium-coated silicon substrate is performed to form low resistivity titanium silicide. In preferred processes, the metallic element is indium or gallium, and more preferably the metallic element is indium. A semiconductor device that has a titanium silicide layer on the surface of a silicon substrate is also provided.

A method is provided for forming NMOS and PMOS transistors with ultra shallow source / drain regions having high dopant concentrations. First sidewall spacers and nitride spacers are sequentially formed on the sides of a gate electrode followed by forming a self-aligned oxide etch stop layer. The nitride spacer is removed and an amorphous silicon layer is deposited. The etch stop layer enables a controlled etch of the amorphous silicon layer to form silicon sidewalls on the first sidewall spacers. Implant steps are followed by an RTA to activate shallow and deep S / D regions. The etch stop layer maintains a high dopant concentration in deep S / D regions. After the etch stop is removed and a titanium layer is deposited on the substrate, an RTA forms a titanium silicide layer on the gate electrode and an extended silicide layer over the silicon sidewalls and substrate which results in a low resistivity.

A titanium silicide film is formed on an Si wafer. At first, a plasma process using an RF is performed on the Si wafer. Then, a Ti-containing source gas is supplied onto the Si wafer processed by the plasma process and plasma is generated to form a Ti film. At this time, the Ti silicide film is formed by a reaction of the Ti film with Si of the Si wafer. The plasma process is performed on the Si wafer while the Si wafer is supplied with a DC bias voltage having an absolute value of 200V or more.

An arrangement of elongated nanowires that include titanium silicide or tungsten silicide may be grown on the exterior surfaces of many individual electrically conductive microfibers of much larger diameter. Each of the nanowires is structurally defined by an elongated, centralized titanium silicide or tungsten silicide nanocore that terminates in a distally spaced gold particle and which is co-axially surrounded by a removable amorphous nanoshell. A gold-directed catalytic growth mechanism initiated during a low pressure chemical vapor deposition process is used to grow the nanowires uniformly along the entire length and circumference of the electrically conductive microfibers where growth is intended. The titanium silicide- or tungsten silicide-based nanowires can be used in a variety electrical, electrochemical, and semiconductor applications.

The invention discloses an electrode active material for a lead-acid storage battery. The electrode active material comprises lead powder and a non-metallic titanium compound; the lead powder comprises one or more kinds of metal lead powder, ball-milling lead powder, Barton lead powder, Pb<2>O powder, PbO powder, Pb<2>O<3> powder, Pb<3>O<4> powder and PbO<2> powder; and the non-metallic titanium compound comprises one or more kinds of titanium sulfide, titanium nitride, titanium boride, titanium carbide, titanium hydride, titanium hydroxide, titanium silicide, a symbiotic blend of the abovementioned compounds on an atomic micro level or atomic cluster level, and doped compounds formed by doping the abovementioned compounds with one or more kinds of F, Sb, Sn, Ca, Bi, Co, Ca, Al, Mg, N, P, O and C. By virtue of the electrode active material for the lead-acid storage battery with an improved formula, the specific power, specific energy, charging-discharging efficiency, cycle life, low-temperature performance and the like of the lead-acid storage battery can be obviously improved.

A method is described for forming a thin film transistor having its current-switching region in polycrystalline semiconductor material which has been crystallized in contact with titanium silicide, titanium silicide-germanide, or titanium germanide. The titanium silicide, titanium silicide-germanide, or titanium germanide is formed having feature size no more than 0.25 micron in the smallest dimension. The small feature size tends to inhibit the phase transformation from C49 to C54 phase titanium silicide. The C49 phase of titanium silicide has a very close lattice match to silicon, and thus provides a crystallization template for the silicon as it forms, allowing formation of large-grain, low-defect silicon. Titanium does not tend to migrate through the silicon during crystallization, limiting the danger of metal contamination. In preferred embodiments, the transistors thus formed may be, for example, field-effect transistors or bipolar junction transistors.

A method for radio frequency lateral diffusing self-alignment silicides of the field-effect-transistor, comprising the steps of: on the silicon chips, injecting the etched multiple crystal grids to the drifting zone without mask; depositing a thin silicon dioxide layer with tetraethylorthosilicate heat decomposition method; protecting drifting zone with photo resist and resisting silicon dioxide, forming a silicon dioxide sidewall on the gate side nearby the source; source-drain self-aligning injection and striping; quick heat annealing to eliminate injection damage and activate impurity; separately depositing a thin pad silicon dioxide with tetraethylorthosilicate heat decomposition method and depositing a silicon nitride with low pressure chemical vapour deposition method; sequentially resisting silicon nitride and silicon dioxide, forming a silicon nitride secondary sidewall on the silicon dioxide primary sidewall; sputtering a thin titanium layer; quick heat annealing to form the titanium silicides from the silicon and titanium; etching and removing the rest titanium; quick heat annealing to forming low resistance titanium silicides from high resistance ones.

A high-efficiency power semiconductor rectifier device (10) comprising a δP++ layer (12), a P-body (14), an N-drift region (16), an N+ substrate (18), an anode (20), and a cathode (22). The method of fabricating the device (10) comprises the steps of depositing the N-drift region (16) on the N+ substrate (18), implanting boron into the N-drift region (16) to create a P-body region (14), forming a layer of titanium silicide (56) on the P-body region (14), and concentrating a portion of the implanted boron at the interface region between the layer of titanium silicide (56) and the P-body region (14) to create the δP++ layer (12) of supersaturated P-doped silicon.

The invention discloses a refinement modifier for hypoeutectic aluminum-silicon cast alloy, and a preparation method and the application thereof. The refinement modifier for hypoeutectic aluminum-silicon cast alloy is characterized by comprising the chemical ingredients of Al-1Ti-3B-10RE which are, by weight, 0.9% to 1.1% of Ti, 2.8% to 3.2% of B, 10% to 12% of RE, and the balance Al. The RE comprises the ingredients of 40% of mixed light rare earth rich in La, and 60% of Y. The problem of (Al and Ti)B2 and AlB2 agglomeration in a refinement modifier is solved due to the active roles of rare earth elements in cooperation with fusion magnetic blending and quick solidification. Compared with the widely used refinement modifier Al-5Ti-1B and the widely used refinement modifier Al-10Sr, the refinement modifier for hypoeutectic aluminum-silicon cast alloy has the function of integrating refinement and modification, and is easy to apply; andthe titanium silicide poisoning refinement effect or the phenomenon that air intake of alloy melt is intensified by Sr or the phenomenon that Sr and B poison each other does not exist, and the effect of refining alpha-Al and the mechanical property ofalloy can be obviously improved.

The invention includes an electrically conductive line, methods of forming electrically conductive lines, and methods of reducing titanium silicide agglomeration in the fabrication of titanium silicide over polysilicon transistor gate lines. In one implementation, a method of forming an electrically conductive line includes providing a silicon-comprising layer over a substrate. An electrically conductive layer is formed over the silicon-comprising layer. An MSixNy-comprising layer is formed over the electrically conductive layer, where “x” is from 0 to 3.0, “y” is from 0.5 to 10, and “M” is at least one of Ta, Hf, Mo, and W. An MSiz-comprising layer is formed over the MSixNy-comprising layer, where “z” is from 1 to 3.0. A TiSia-comprising layer is formed over the MSiz-comprising layer, where “a” is from 1 to 3.0. The silicon-comprising layer, the electrically conductive layer, the MSixNy-comprising layer, the MSiz-comprising layer, and the TiSia-comprising layer are patterned into a stack comprising an electrically conductive line. Other aspects and implementations are contemplated.

An insulation film having an open part in which a silicon part is exposed at a bottom surface is formed on a silicon substrate for forming a semiconductor device. Titanium is deposited to form a titanium film on the bottom surface and side wall surfaces of the contact hole. The silicon substrate and the titanium film are reacted with each other by a first annealing process to form a titanium silicide film on the bottom surface. After the titanium film that remains on the side wall surfaces of the contact hole is removed, a hydrogen annealing process is performed. This hydrogen annealing reduces the density of the interface level in the interface between the silicon substrate, the gate insulation film on the substrate surface, or the like, and improves the characteristics of the semiconductor device. After the hydrogen annealing, tungsten is deposited in the remaining space of the contact hole to form a tungsten plug. According to this manufacturing method, since a barrier metal composed of a titanium film is not formed on the bottom surface and side wall surfaces of the contact hole, trapping of hydrogen by titanium is suppressed, and hydrogen annealing is effectively performed.

The invention provides a power device with a high-voltage radio-frequency lateral diffusion structure and a production method of the power device. The production method comprises the steps of providing a P-type substrate, on which a P-type epitaxial layer is arranged; forming a P-type depressed region and a plurality of local oxide isolations on the epitaxial layer; thermally growing gate oxide and phosphor-doped polycrystalline silicon gate to form a grid; respectively filling boron on the two sides of the grid to form a P-type body region, filling phosphor to form an N-type drift region, push-connecting the P-type body region with the N-type drift region at high temperature; respectively filling boron in the P-type depressed region to form a P+ region, filling arsenic in the P-type body region and the N-type drift region to form an N+ region and annealing at high temperature; generating an oxide-nitride-oxide (ONO) structure on the surface of a device, etching through a dry process and obtaining D-shaped side walls on the two sides of the grid; removing silicon dioxide on the surfaces of the side walls and obtaining L-shaped side walls; forming a barrier layer on the surface of the device and opening a window above the grid; and forming titanium silicide contact above the grid. The power device with the high-voltage radio-frequency lateral diffusion structure and the production method of the power device have the advantages that the risks that the source is short-circuited with the drain can be effectively avoided, the grid silicide with very low resistivity can be obtained and the demands of high-frequency lateral diffusion metal-oxide-semiconductor field-effect transistors (LDMOS) can be met.

A composition of matter is generally provided, in one embodiment, a titanium alloy comprising about 5 wt % to about 8 wt % aluminum; about 2.5 wt % to about 5.5 wt % vanadium; about 0.1 wt % to about 2 wt % of one or more elements selected from the group consisting of iron and molybdenum; about 0.01 wt % to about 0.2 wt % carbon; up to about 0.3 wt % oxygen; silicon and copper; and titanium. A turbine component is also generally provided, in one embodiment, that comprises an article made from a titanium alloy. Additionally, methods are also generally provided for making an alloy component having a beta transus temperature and a titanium silicide solvus temperature.

A structure comprising silicon-containing ceramic body and an active metal-containing metal layer as a brazing layer or a metallization layer bonded to and disposed on the surface of the ceramic body. A reaction layer of a compound containing constituent elements of the ceramic body and the active metal is formed in the interface between the ceramic body and the metal layer. The reaction layer is present ahead the outer circular edge of the metal layer. In particular, when the ceramic body is silicon nitride with the active metal being titanium, the reaction layer comprises a first reaction layer composed mainly of titanium nitride and a second reaction layer composed mainly of titanium silicide. The first reaction layer is present ahead the outer circular edge of the second reaction layer. According to the brazed structure and the metallized structure, the characteristics of the metal layer containing the active metal, such as bonding strength, can be improved with good reproducibility.

A method of forming a titanium silicide nitride (TiSiN) layer on a substrate id described. The titanium silicide nitride (TiSiN) layer is formed by providing a substrate to a process chamber and treating the substrate with a silicon-containing gas. A titanium nitride layer is formed on the treated substrate and exposed to a silicon-containing gas. The titanium nitride (TiN) layer reacts with the silicon-containing gas to form the titanium silicide nitride (TiSiN) layer. The formation of the titanium silicide nitride (TiSiN) layer is compatible with integrated circuit fabrication processes. In one integrated circuit fabrication process, the titanium silicide nitride (TiSiN) layer may be used as a diffusion barrier for a tungsten (W) metallization process.

The technical proposal discloses a titanium alloy composite material. The titanium alloy composite material is prepared from titanium alloy powder and reinforcing phase powder, wherein the reinforcingphase powder is prepared from titanium carbide, titanium boride and titanium silicide, and the weight fraction of reinforcing phase powder accounts for the titanium alloy composite material is 0.5%-20%. According to the technical scheme, a ball milling method is adopted to insert titanium carbide, titanium boride and boron carbide powder into the titanium alloy powder to form a composite powder material of titanium alloy and titanium carbide, titanium boride and boron carbide, so that the hardness and strength of the titanium alloy material is greatly improved. And meanwhile, the prepared composite powder is subjected to laser additive manufacturing forming, by regulating laser manufacturing parameters, metallurgical defects such as cracks and pores of the titanium alloy composite material during laser manufacturing are reduced or eliminated, and the comprehensive mechanical properties such as density, hardness and strength of parts are significantly improved, and the problem of difficult to manufacture the titanium alloy material is solved.

The invention relates to a method for synthesizing titanium silicide (Ti5Si3) granule in original position to intensify the composite material based on titanium carbide aluminum (Ti3AlC2). Adding a certain amount of silicon, to prepare the Ti3AlC2 / Ti5Si3 composite material of different volume ratio, the volume percentage of the titanium silicide granule is 10-40%. The specific preparing method comprises: employing titanium powder, aluminium powder, silicon powder and graphite powder as raw material, the mole ratio of Tií†Alí†Sií†C is 3: (1.1-x): (1.8~2.0), and x is 0.1-0.5, mixing the raw material powder with physical-mechanical means for 8-24 hours, loading into the graphite mould, the forced pressure is 10-20 Mpa, calcinating in the heating furnace under protective atmosphere, the heating-up speed is 10-50 Deg C / min, the calcining temperature is 1400-1600 Deg C and lasting for 0.5-2 hours, the calcinating pressure is 20-40 Mpa. The titanium carbide aluminium / titanium silicide of high purity and high intensity can be produced under lower temperature and in shorter time by applying this invention.

The invention discloses a multiphase particle enhanced powder metallurgical titanium-based composite material and a preparation method thereof. The material comprises three or more of titanium boride, titanium carbide, titanium silicide and titanium silicon carbide. The method comprises the following steps of: weighing titanium powder, boron carbide powder, silicon carbide powder and alloying element powder with certain granularity according to the weight percent ratio of components; uniformly mixing the powder by a mixing method; pressing into a blank with a certain shape by a compression molding process; putting the blank into a vacuum hot-pressing sintering furnace for sintering; and cooling with the furnace to obtain in-situ synthesized multiphase particle enhanced powder metallurgical titanium-based composite material. The process is simple, the boron carbide powder and the silicon carbide powder in different ratios are added during mixing, and the multiphase particle dispersion enhanced titanium-based composite material which comprises the titanium boride, the titanium carbide, the titanium silicide, the titanium silicon carbide and the like is generated through in-situ reaction. The material meets the requirements of aerospace, an advanced weapon system, an automobile engine and the like on high specific strength, high specific rigidity, wear resistance and corrosion resistance.

A first layer of titanium nitride (TiN) is formed on a semiconductor structure, such as an interconnect via. Then, a second layer of TiN is formed on the first layer of TiN. The first layer of TiN is amorphous. The second layer of TiN is polycrystalline, having a mixed grain orientation. Finally, an aluminum film is formed on the second layer of titanium nitride. Optionally, a titanium silicide layer is formed on the semiconductor structure prior to the step of forming the first layer of titanium nitride. Interconnects formed according to the invention have polycrystalline aluminum films with grain sizes of approximately less than 0.25 microns.