Processing unit interface for intellectual property (IP) core and automatic generation method thereof

Abstract

The invention discloses a processing unit interface for an intellectual property (IP) core and an automatic generation method thereof. The processing unit interface comprises an interface protocol module and a data buffer synchronization unit, wherein the data buffer synchronization unit is used for data buffer and clock synchronization. The automatic generation method comprises the following implementation steps of: 1) obtaining the interface description information of the IP core; 2) obtaining the data width of the IP core according to interface lead pin information, obtaining the work efficiency of the IP core according to clock signal information, and generating a complementary time sequence state machine according to an interface time sequence rule; 3) generating a clock synchronization module when the work frequency of the IP core is different from the work frequency of the processing unit; 4) generating data buffer module codes when the data width of the IP core is different from the data width of the processing unit; and 5) generating the interface protocol module according to the interface lead pin information, the lead pin mapping information and the complementary time sequence state machine. The processing unit interface has the advantages that the universality is good, the development is fast and convenient, and the compatibility with the IP core and the processing unit is good.

Description

technical field [0001] The invention relates to the technical field of processor development, in particular to a processor interface for an IP core and a method for automatically generating Register Transfer Level (RTL) codes. Background technique [0002] With the rapid development of semiconductor manufacturing technology, the scale of the processor is getting larger and larger, and the design complexity of the processor is also increasing. IP core (Intellectual Property core) is a hardware description language program with specific circuit functions. This program has nothing to do with the integrated circuit process and can be transplanted to different semiconductor processes to produce integrated circuit chips. Therefore, the existing IP core is reused. The design and verification time of the processor can be effectively saved, the time to market of the processor can be greatly shortened, and the development cost of the processor can be reduced. [0003] The interface p...

AI Technical Summary

Problems solved by technology

However, on the one hand, because the idea of ​​VCI appeared late, and it was only proposed by a third-party organization to provide the Wrapper of common protocols, many existing IP cores are not compatible with the VCI protocol, and the interfaces of existing IP cores must be redesigned. The design must comply with the VCI protocol, which is obviously not realistic

On the other hand, the VCI protocol exists as an intermediate protocol between the IP core and the processor, which also reduces the performance of the interface between the IP core and the processor

Therefore, the method based on the VCI protocol has the problems of poor compatibility and low interface efficiency

Images